| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 1259 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ); in LowerSHL_PARTS() local
1260 LoBitsForHi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, LoBitsForHi); in LowerSHL_PARTS()
1270 SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE); in LowerSHL_PARTS()
1272 DAG.getSelect(dl, MVT::i32, SetCC, HiForBigShift, HiForNormalShift); in LowerSHL_PARTS()
1278 dl, MVT::i32, SetCC, DAG.getConstant(0, dl, MVT::i32), LoForNormalShift); in LowerSHL_PARTS()
1307 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE); in LowerSRL_PARTS() local
1310 Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi); in LowerSRL_PARTS()
1313 Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo); in LowerSRL_PARTS()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrCMovSetCC.td | 1 //===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===//
75 // SetCC instructions.
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| H A D | X86ISelLowering.cpp | 23586 SDValue SetCC = getSETCC(Cond, Overflow, DL, DAG); in LowerXALUO() local
23588 return DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(), Value, SetCC); in LowerXALUO()
25468 SDValue SetCC; in LowerINTRINSIC_WO_CHAIN() local
25471 SetCC = getSETCC(X86::COND_E, Comi, dl, DAG); in LowerINTRINSIC_WO_CHAIN()
25473 SetCC = DAG.getNode(ISD::AND, dl, MVT::i8, SetCC, SetNP); in LowerINTRINSIC_WO_CHAIN()
25477 SetCC = getSETCC(X86::COND_NE, Comi, dl, DAG); in LowerINTRINSIC_WO_CHAIN()
25479 SetCC = DAG.getNode(ISD::OR, dl, MVT::i8, SetCC, SetP); in LowerINTRINSIC_WO_CHAIN()
25484 SetCC = getSETCC(X86::COND_A, Comi, dl, DAG); in LowerINTRINSIC_WO_CHAIN()
25489 SetCC = getSETCC(X86::COND_AE, Comi, dl, DAG); in LowerINTRINSIC_WO_CHAIN()
25494 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); in LowerINTRINSIC_WO_CHAIN()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 680 SDValue SetCC = N->getOperand(0); in performSELECTCombine() local
682 if ((SetCC.getOpcode() != ISD::SETCC) || in performSELECTCombine()
683 !SetCC.getOperand(0).getValueType().isInteger()) in performSELECTCombine()
707 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
710 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), in performSELECTCombine()
711 SetCC.getOperand(1), in performSELECTCombine()
712 ISD::getSetCCInverse(CC, SetCC.getValueType())); in performSELECTCombine()
714 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); in performSELECTCombine()
737 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); in performSELECTCombine()
744 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
[all …]
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| H A D | MipsSEISelLowering.cpp | 985 SDValue SetCC = N->getOperand(0); in performVSELECTCombine() local
987 if (SetCC.getOpcode() != MipsISD::SETCC_DSP) in performVSELECTCombine()
991 SetCC.getOperand(0), SetCC.getOperand(1), in performVSELECTCombine()
992 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2)); in performVSELECTCombine()
|
| H A D | MipsInstrInfo.td | 1515 // SetCC
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrPrefix.td | 2440 multiclass IntSetP10RevSetBool<SDNode SetCC, ValueType Ty, PatLeaf ZExtTy,
2443 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
2445 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
2447 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
2449 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
2451 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
2454 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETUGE)),
2456 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETGE)),
2458 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETULE)),
2460 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETLE)),
[all …]
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| H A D | PPCInstrInfo.td | 4075 multiclass FSetCCPat<SDPatternOperator SetCC, ValueType Ty, I FCmp> {
4076 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
4078 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
4080 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
4082 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
4084 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)),
4086 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
4088 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)),
4091 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOLT)),
4093 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLT)),
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 1402 SDValue SetCC = DAG.getNode(M68kISD::SETCC, DL, N->getValueType(1), in LowerXALUO() local
1406 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Arith, SetCC); in LowerXALUO()
1937 SDValue SetCC = in LowerSETCC() local
1941 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in LowerSETCC()
1942 return SetCC; in LowerSETCC()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 2188 SDValue SetCC = Z.getOperand(0); in foldAddSubBoolOfMaskedVal() local
2189 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get(); in foldAddSubBoolOfMaskedVal()
2190 if (CC != ISD::SETEQ || !isNullConstant(SetCC.getOperand(1)) || in foldAddSubBoolOfMaskedVal()
2191 SetCC.getOperand(0).getOpcode() != ISD::AND || in foldAddSubBoolOfMaskedVal()
2192 !isOneConstant(SetCC.getOperand(0).getOperand(1))) in foldAddSubBoolOfMaskedVal()
2201 SDValue LowBit = DAG.getZExtOrTrunc(SetCC.getOperand(0), DL, VT); in foldAddSubBoolOfMaskedVal()
7781 SDValue SetCC = in visitXOR() local
7784 CombineTo(N, SetCC); in visitXOR()
7785 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), SetCC.getValue(1)); in visitXOR()
10400 for (SDNode *SetCC : SetCCs) { in ExtendSetCCUses()
[all …]
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| H A D | LegalizeIntegerTypes.cpp | 1085 SDValue SetCC; in PromoteIntRes_SETCC() local
1090 SetCC = DAG.getNode(N->getOpcode(), dl, VTs, Opers); in PromoteIntRes_SETCC()
1093 ReplaceValueWith(SDValue(N, 1), SetCC.getValue(1)); in PromoteIntRes_SETCC()
1095 SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0), in PromoteIntRes_SETCC()
1099 return DAG.getSExtOrTrunc(SetCC, dl, NVT); in PromoteIntRes_SETCC()
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| H A D | TargetLowering.cpp | 8327 SDValue SetCC = DAG.getSetCC(dl, SetCCType, Result, LHS, CC); in expandUADDSUBO() local
8328 Overflow = DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType); in expandUADDSUBO()
8349 SDValue SetCC = DAG.getSetCC(dl, OType, Result, Sat, ISD::SETNE); in expandSADDSUBO() local
8350 Overflow = DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType); in expandSADDSUBO()
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| H A D | SelectionDAGBuilder.cpp | 7105 SDValue SetCC = DAG.getSetCC(DL, CCVT, VectorInduction.getValue(0), in visitIntrinsicCall() local
7109 SetCC)); in visitIntrinsicCall()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 4704 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, DL, CCVT, LHS, RHS, in lowerICMPIntrinsic() local
4707 return SetCC; in lowerICMPIntrinsic()
4708 return DAG.getZExtOrTrunc(SetCC, DL, VT); in lowerICMPIntrinsic()
4734 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0, in lowerFCMPIntrinsic() local
4737 return SetCC; in lowerFCMPIntrinsic()
4738 return DAG.getZExtOrTrunc(SetCC, SL, VT); in lowerFCMPIntrinsic()
4977 SDNode *SetCC = nullptr; in LowerBRCOND() local
4981 SetCC = Intr; in LowerBRCOND()
4982 Intr = SetCC->getOperand(0).getNode(); in LowerBRCOND()
5000 assert(!SetCC || in LowerBRCOND()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 3700 SDValue SetCC = emitSETCC(DAG, DL, Result.getValue(1), CCValid, CCMask); in lowerXALUO() local
3702 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in lowerXALUO()
3704 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC); in lowerXALUO()
3766 SDValue SetCC = emitSETCC(DAG, DL, Result.getValue(1), CCValid, CCMask); in lowerADDSUBCARRY() local
3768 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in lowerADDSUBCARRY()
3770 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC); in lowerADDSUBCARRY()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 1964 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, ResTy, in WidenHvxSetCC() local
1969 {SetCC, getZero(dl, MVT::i32, DAG)}); in WidenHvxSetCC()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 15397 SDValue SetCC = N->getOperand(0); in performVSelectCombine() local
15398 if (SetCC.getOpcode() == ISD::SETCC && in performVSelectCombine()
15399 SetCC.getOperand(2) == DAG.getCondCode(ISD::SETGT)) { in performVSelectCombine()
15400 SDValue CmpLHS = SetCC.getOperand(0); in performVSelectCombine()
15402 SDNode *CmpRHS = SetCC.getOperand(1).getNode(); in performVSelectCombine()
15441 SetCC = DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(), in performVSelectCombine()
15444 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC, in performVSelectCombine()
15504 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2)); in performSelectCombine() local
15508 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask); in performSelectCombine()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 12475 SDValue SetCC; in PerformSELECTCombine() local
12484 SetCC = N->getOperand(0); in PerformSELECTCombine()
12485 LHS = SetCC->getOperand(0); in PerformSELECTCombine()
12486 RHS = SetCC->getOperand(1); in PerformSELECTCombine()
12487 CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get(); in PerformSELECTCombine()
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