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Searched refs:SchedClass (Results 1 – 19 of 19) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/MC/
H A DMCSchedule.cpp57 unsigned SchedClass) const { in computeInstrLatency()
58 const MCSchedClassDesc &SCDesc = *getSchedClassDesc(SchedClass); in computeInstrLatency()
70 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass(); in computeInstrLatency() local
71 const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass); in computeInstrLatency()
77 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID); in computeInstrLatency()
78 SCDesc = getSchedClassDesc(SchedClass); in computeInstrLatency()
81 if (SchedClass) in computeInstrLatency()
113 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass(); in getReciprocalThroughput() local
114 const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass); in getReciprocalThroughput()
123 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID); in getReciprocalThroughput()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonDepTimingClasses.h19 inline bool is_TC1(unsigned SchedClass) { in is_TC1() argument
20 switch (SchedClass) { in is_TC1()
66 inline bool is_TC2(unsigned SchedClass) { in is_TC2() argument
67 switch (SchedClass) { in is_TC2()
98 inline bool is_TC2early(unsigned SchedClass) { in is_TC2early() argument
99 switch (SchedClass) { in is_TC2early()
108 inline bool is_TC3x(unsigned SchedClass) { in is_TC3x() argument
109 switch (SchedClass) { in is_TC3x()
139 inline bool is_TC4x(unsigned SchedClass) { in is_TC4x() argument
140 switch (SchedClass) { in is_TC4x()
H A DHexagonInstrInfo.cpp2182 unsigned SchedClass = MI.getDesc().getSchedClass(); in isEarlySourceInstr() local
2183 return is_TC4x(SchedClass) || is_TC3x(SchedClass); in isEarlySourceInstr()
2374 unsigned SchedClass = MI.getDesc().getSchedClass(); in isLateResultInstr() local
2375 return !is_TC1(SchedClass); in isLateResultInstr()
2623 unsigned SchedClass = MI.getDesc().getSchedClass(); in isTC1() local
2624 return is_TC1(SchedClass); in isTC1()
2628 unsigned SchedClass = MI.getDesc().getSchedClass(); in isTC2() local
2629 return is_TC2(SchedClass); in isTC2()
2633 unsigned SchedClass = MI.getDesc().getSchedClass(); in isTC2Early() local
2634 return is_TC2early(SchedClass); in isTC2Early()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTargetSchedule.cpp135 unsigned SchedClass = MI->getDesc().getSchedClass(); in resolveSchedClass() local
136 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass); in resolveSchedClass()
146 SchedClass = STI->resolveSchedClass(SchedClass, MI, this); in resolveSchedClass()
147 SCDesc = SchedModel.getSchedClassDesc(SchedClass); in resolveSchedClass()
327 unsigned SchedClass = MI->getDesc().getSchedClass(); in computeReciprocalThroughput() local
328 return MCSchedModel::getReciprocalThroughput(SchedClass, in computeReciprocalThroughput()
340 unsigned SchedClass = TII->get(Opcode).getSchedClass(); in computeReciprocalThroughput() local
342 return MCSchedModel::getReciprocalThroughput(SchedClass, in computeReciprocalThroughput()
345 const MCSchedClassDesc &SCDesc = *SchedModel.getSchedClassDesc(SchedClass); in computeReciprocalThroughput()
H A DMachinePipeliner.cpp998 unsigned SchedClass = Inst->getDesc().getSchedClass(); in minFuncUnits() local
1002 make_range(InstrItins->beginStage(SchedClass), in minFuncUnits()
1003 InstrItins->endStage(SchedClass))) { in minFuncUnits()
1015 STI->getSchedModel().getSchedClassDesc(SchedClass); in minFuncUnits()
1045 unsigned SchedClass = MI.getDesc().getSchedClass(); in calcCriticalResources() local
1048 make_range(InstrItins->beginStage(SchedClass), in calcCriticalResources()
1049 InstrItins->endStage(SchedClass))) { in calcCriticalResources()
1058 STI->getSchedModel().getSchedClassDesc(SchedClass); in calcCriticalResources()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.h122 if (!SU->SchedClass && SchedModel->hasInstrSchedModel()) in getSchedClass()
123 SU->SchedClass = SchedModel->resolveSchedClass(SU->getInstr()); in getSchedClass()
124 return SU->SchedClass; in getSchedClass()
H A DSystemZScheduleZ196.td103 // resources that it needs. These will be combined into a SchedClass.
H A DSystemZScheduleZEC12.td106 // resources that it needs. These will be combined into a SchedClass.
H A DSystemZScheduleZ13.td122 // resources that it needs. These will be combined into a SchedClass.
H A DSystemZScheduleZ14.td122 // resources that it needs. These will be combined into a SchedClass.
H A DSystemZScheduleZ15.td122 // resources that it needs. These will be combined into a SchedClass.
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DScheduleDAGInstrs.h266 if (!SU->SchedClass && SchedModel.hasInstrSchedModel()) in getSchedClass()
267 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr()); in getSchedClass()
268 return SU->SchedClass; in getSchedClass()
H A DTargetSubtargetInfo.h140 virtual unsigned resolveSchedClass(unsigned SchedClass, in resolveSchedClass() argument
H A DScheduleDAG.h253 const MCSchedClassDesc *SchedClass = variable
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp428 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); in getCVIResources() local
429 int Size = II[SchedClass].LastStage - II[SchedClass].FirstStage; in getCVIResources()
435 unsigned Stage = II[SchedClass].LastStage - 1; in getCVIResources()
447 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); in getUnits() local
448 return ((II[SchedClass].FirstStage + HexagonStages)->getUnits()); in getUnits()
458 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); in getOtherReservedSlots() local
464 for (unsigned Stage = II[SchedClass].FirstStage + 1; in getOtherReservedSlots()
465 Stage < II[SchedClass].LastStage; ++Stage) { in getOtherReservedSlots()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/
H A DMCInstrDesc.h201 unsigned short SchedClass; // enum identifying instr sched class variable
612 unsigned getSchedClass() const { return SchedClass; } in getSchedClass()
H A DMCSchedule.h368 getReciprocalThroughput(unsigned SchedClass, const InstrItineraryData &IID);
H A DMCSubtargetInfo.h219 virtual unsigned resolveVariantSchedClass(unsigned SchedClass, in resolveVariantSchedClass() argument
/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp1313 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx); in EmitSchedClassTables() local
1314 OS << " {DBGFIELD(\"" << SchedClass.Name << "\") "; in EmitSchedClassTables()
1315 if (SchedClass.Name.size() < 18) in EmitSchedClassTables()
1316 OS.indent(18 - SchedClass.Name.size()); in EmitSchedClassTables()