| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 271 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || in getArithmeticInstrCost()
276 if (ISD == ISD::SDIV || ISD == ISD::SREM) { in getArithmeticInstrCost()
294 if (ISD == ISD::SREM) { in getArithmeticInstrCost()
342 { ISD::SREM, MVT::v16i32, 8 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
362 { ISD::SREM, MVT::v8i32, 8 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
384 { ISD::SREM, MVT::v8i32, 16+2 }, // 2*pmuludq+mul+sub sequence + split. in getArithmeticInstrCost()
386 { ISD::SREM, MVT::v4i32, 8 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
403 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
407 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence in getArithmeticInstrCost()
422 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence in getArithmeticInstrCost()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMTargetTransformInfo.cpp | 1278 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
1282 { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1286 { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
1290 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
1295 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1299 { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
1303 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
1307 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
1808 case ISD::SREM: in maybeLoweredToCall()
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| H A D | ARMISelLowering.cpp | 211 setOperationAction(ISD::SREM, VT, Expand); in addTypeForNEON()
289 setOperationAction(ISD::SREM, VT, Expand); in addMVEVectorTypes()
1192 setOperationAction(ISD::SREM, MVT::i32, Expand); in ARMTargetLowering()
1199 setOperationAction(ISD::SREM, MVT::i64, Custom); in ARMTargetLowering()
9879 case ISD::SREM: return LowerREM(Op.getNode(), DAG); in LowerOperation()
10005 case ISD::SREM: in ReplaceNodeResults()
18677 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) && in getDivRemLibcall()
18680 N->getOpcode() == ISD::SREM; in getDivRemLibcall()
18695 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) && in getDivRemArgList()
18698 N->getOpcode() == ISD::SREM; in getDivRemArgList()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 237 SREM, enumerator
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| H A D | TargetLowering.h | 2464 case ISD::SREM: in isBinOp()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 1929 case ISD::SREM: in selectDivRem()
1950 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM) in selectDivRem()
2051 if (!selectBinaryOp(I, ISD::SREM)) in fastSelectInstruction()
2052 return selectDivRem(I, ISD::SREM); in fastSelectInstruction()
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| H A D | MipsSEISelLowering.cpp | 242 setOperationAction(ISD::SREM, MVT::i32, Legal); in MipsSETargetLowering()
289 setOperationAction(ISD::SREM, MVT::i64, Legal); in MipsSETargetLowering()
340 setOperationAction(ISD::SREM, Ty, Legal); in addMSAIntType()
2057 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 370 case ISD::SREM: in LegalizeOp()
900 case ISD::SREM: in Expand()
1444 assert((Node->getOpcode() == ISD::SREM || Node->getOpcode() == ISD::UREM) && in ExpandREM()
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| H A D | SelectionDAGBuilder.h | 696 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); } in visitSRem()
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| H A D | SelectionDAGDumper.cpp | 236 case ISD::SREM: return "srem"; in getOperationName()
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| H A D | LegalizeDAG.cpp | 3253 case ISD::SREM: in ExpandNode()
4301 case ISD::SREM: in ConvertNodeToLibcall()
4489 case ISD::SREM: in PromoteNode()
4507 case ISD::SREM: in PromoteNode()
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| H A D | SelectionDAG.cpp | 3379 case ISD::SREM: { in computeKnownBits()
4010 case ISD::SREM: in ComputeNumSignBits()
5084 case ISD::SREM: in FoldValue()
5116 case ISD::SREM: in isUndef()
5567 case ISD::SREM: in getNode()
5899 case ISD::SREM: in getNode()
5921 case ISD::SREM: in getNode()
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| H A D | LegalizeVectorTypes.cpp | 141 case ISD::SREM: in ScalarizeVectorResult()
1032 case ISD::SREM: in SplitVectorResult()
3045 case ISD::SREM: in WidenVectorResult()
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| H A D | FastISel.cpp | 1702 return selectBinaryOp(I, ISD::SREM); in selectOperator()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 137 setOperationAction(ISD::SREM, MVT::i8, Promote); in MSP430TargetLowering()
143 setOperationAction(ISD::SREM, MVT::i16, LibCall); in MSP430TargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 912 case ISD::SREM: in canOpTrap()
1765 case SRem: return ISD::SREM; in InstructionOpcodeToISD()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 105 setOperationAction(ISD::SREM, VT, Expand); in BPFTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 507 setTargetDAGCombine(ISD::SREM); in NVPTXTargetLowering()
4515 assert(N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM); in PerformREMCombine()
4524 bool IsSigned = N->getOpcode() == ISD::SREM; in PerformREMCombine()
4743 case ISD::SREM: in PerformDAGCombine()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 151 setOperationAction(ISD::SREM, MVT::i8, Expand); in AVRTargetLowering()
152 setOperationAction(ISD::SREM, MVT::i16, Expand); in AVRTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 4533 case ISD::SREM: in selectRem()
5029 if (!selectBinaryOp(I, ISD::SREM)) in fastSelectInstruction()
5030 return selectRem(I, ISD::SREM); in fastSelectInstruction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 110 setOperationAction(ISD::SREM, MVT::i32, Expand); in LanaiTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 303 setOperationAction(ISD::SREM, MVT::i32, Legal); in PPCTargetLowering()
305 setOperationAction(ISD::SREM, MVT::i64, Legal); in PPCTargetLowering()
308 setOperationAction(ISD::SREM, MVT::i32, Expand); in PPCTargetLowering()
310 setOperationAction(ISD::SREM, MVT::i64, Expand); in PPCTargetLowering()
788 setOperationAction(ISD::SREM, VT, Expand); in PPCTargetLowering()
911 setOperationAction(ISD::SREM, MVT::v2i64, Legal); in PPCTargetLowering()
913 setOperationAction(ISD::SREM, MVT::v4i32, Legal); in PPCTargetLowering()
915 setOperationAction(ISD::SREM, MVT::v1i128, Legal); in PPCTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1584 {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM, in HexagonTargetLowering()
1631 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::SADDO, in HexagonTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1499 setOperationAction(ISD::SREM, MVT::i32, Expand); in SparcTargetLowering()
1506 setOperationAction(ISD::SREM, MVT::i64, Expand); in SparcTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 200 ISD::SREM, ISD::UREM, ISD::ROTL, ISD::ROTR}) in WebAssemblyTargetLowering()
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