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Searched refs:SOffset (Results 1 – 15 of 15) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp758 MachineOperand *SOffset = TII->getNamedOperand(MI, AMDGPU::OpName::soffset); in resolveFrameIndex() local
759 assert(SOffset->isImm() && SOffset->getImm() == 0); in resolveFrameIndex()
1039 MCRegister SOffset = ScratchOffsetReg; in buildSpillLoadStore() local
1072 if (!IsOffsetLegal || (IsFlat && !SOffset && !ST.hasFlatScratchSTMode())) { in buildSpillLoadStore()
1073 SOffset = MCRegister(); in buildSpillLoadStore()
1084 SOffset = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0, false); in buildSpillLoadStore()
1088 SOffset = Reg; in buildSpillLoadStore()
1094 if (!SOffset) { in buildSpillLoadStore()
1104 SOffset = ScratchOffsetReg; in buildSpillLoadStore()
1110 if (!SOffset) in buildSpillLoadStore()
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H A DAMDGPUInstructionSelector.h251 Register &SOffset, int64_t &ImmOffset) const;
256 Register &RSrcReg, Register &SOffset,
260 Register &SOffset, int64_t &Offset) const;
H A DAMDGPUISelDAGToDAG.cpp190 SDValue &SOffset, SDValue &Offset, SDValue &Offen,
193 SDValue &SOffset, SDValue &Offset) const;
196 SDValue &SOffset, SDValue &ImmOffset) const;
1389 SDValue &SOffset, SDValue &Offset, in SelectMUBUF() argument
1402 SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32); in SelectMUBUF()
1465 SOffset = in SelectMUBUF()
1474 SDValue &VAddr, SDValue &SOffset, in SelectMUBUFAddr64() argument
1483 if (!SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64)) in SelectMUBUFAddr64()
1521 SDValue &VAddr, SDValue &SOffset, in SelectMUBUFScratchOffen() argument
1545 SOffset = isStackPtrRelative(PtrInfo) in SelectMUBUFScratchOffen()
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H A DAMDGPUInstructionSelector.cpp2387 Register VAddr, RSrcReg, SOffset; in selectG_AMDGPU_ATOMIC_CMPXCHG() local
2391 if (selectMUBUFOffsetImpl(MI.getOperand(1), RSrcReg, SOffset, Offset)) { in selectG_AMDGPU_ATOMIC_CMPXCHG()
2395 RSrcReg, SOffset, Offset)) { in selectG_AMDGPU_ATOMIC_CMPXCHG()
2408 if (SOffset) in selectG_AMDGPU_ATOMIC_CMPXCHG()
2409 MIB.addReg(SOffset); in selectG_AMDGPU_ATOMIC_CMPXCHG()
2943 MachineOperand &SOffset = MI.getOperand(5); in selectAMDGPU_BUFFER_ATOMIC_FADD() local
2995 I.add(SOffset); in selectAMDGPU_BUFFER_ATOMIC_FADD()
4066 MachineIRBuilder &B, Register &SOffset, int64_t &ImmOffset) const { in splitIllegalMUBUFOffset() argument
4071 SOffset = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in splitIllegalMUBUFOffset()
4073 .addDef(SOffset) in splitIllegalMUBUFOffset()
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H A DAMDGPURegisterBankInfo.cpp1339 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
1340 if (AMDGPU::splitMUBUFOffset(*Imm, SOffset, ImmOffset, &RBI.Subtarget, in setBufferOffsets()
1343 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0); in setBufferOffsets()
1348 return SOffset + ImmOffset; in setBufferOffsets()
1358 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
1359 if ((int)Offset > 0 && AMDGPU::splitMUBUFOffset(Offset, SOffset, ImmOffset, in setBufferOffsets()
1363 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0); in setBufferOffsets()
1370 if (SOffset == 0) { in setBufferOffsets()
1449 Register SOffset; in applyMappingSBufferLoad() local
1454 VOffset, SOffset, ImmOffset, Alignment); in applyMappingSBufferLoad()
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H A DGCNHazardRecognizer.cpp729 const MachineOperand *SOffset = in createsVALUHazard() local
734 (!SOffset || !SOffset->isReg())) in createsVALUHazard()
H A DSILoadStoreOptimizer.cpp88 bool SOffset = false; member
435 Result.SOffset = true; in getRegs()
461 Result.SOffset = true; in getRegs()
551 if (Regs.SOffset) in setMI()
H A DAMDGPULegalizerInfo.cpp3691 Register SOffset = MI.getOperand(4 + OpOffset).getReg(); in legalizeBufferStore() local
3734 .addUse(SOffset) // soffset in legalizeBufferStore()
3774 Register SOffset = MI.getOperand(4 + OpOffset).getReg(); in legalizeBufferLoad() local
3837 .addUse(SOffset) // soffset in legalizeBufferLoad()
3975 Register SOffset = MI.getOperand(5 + OpOffset).getReg(); in legalizeBufferAtomic() local
4002 .addUse(SOffset) // soffset in legalizeBufferAtomic()
H A DSIInstrInfo.cpp329 const MachineOperand *SOffset = in getMemOperandsWithOffsetWidth() local
331 if (SOffset) { in getMemOperandsWithOffsetWidth()
332 if (SOffset->isReg()) in getMemOperandsWithOffsetWidth()
333 BaseOps.push_back(SOffset); in getMemOperandsWithOffsetWidth()
335 Offset += SOffset->getImm(); in getMemOperandsWithOffsetWidth()
5624 MachineOperand *SOffset = getNamedOperand(MI, AMDGPU::OpName::soffset); in legalizeOperands() local
5639 .add(*SOffset) in legalizeOperands()
5663 .add(*SOffset) in legalizeOperands()
H A DSIISelLowering.cpp6734 SDValue SOffset, in getBufferOffsetForMMO() argument
6738 if (!isa<ConstantSDNode>(VOffset) || !isa<ConstantSDNode>(SOffset) || in getBufferOffsetForMMO()
6748 cast<ConstantSDNode>(SOffset)->getSExtValue() + in getBufferOffsetForMMO()
7868 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
7869 if (AMDGPU::splitMUBUFOffset(Imm, SOffset, ImmOffset, Subtarget, in setBufferOffsets()
7872 Offsets[1] = DAG.getConstant(SOffset, DL, MVT::i32); in setBufferOffsets()
7874 return SOffset + ImmOffset; in setBufferOffsets()
7880 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
7882 if (Offset >= 0 && AMDGPU::splitMUBUFOffset(Offset, SOffset, ImmOffset, in setBufferOffsets()
7885 Offsets[1] = DAG.getConstant(SOffset, DL, MVT::i32); in setBufferOffsets()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCodeEmitter.cpp729 unsigned SOffset = 0; in getMachineOpValue() local
746 ++SOffset; in getMachineOpValue()
772 : SOffset; in getMachineOpValue()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp292 SDValue SOffset = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl); in LowerCall() local
294 ISD::ADD, dl, getPointerTy(DAG.getDataLayout()), StackPtr, SOffset); in LowerCall()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.h889 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
H A DAMDGPUBaseInfo.cpp1890 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, in splitMUBUFOffset() argument
1925 SOffset = Overflow; in splitMUBUFOffset()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp4256 StackOffset &SOffset, in isAArch64FrameOffsetLegal() argument
4303 int64_t Offset = IsMulVL ? SOffset.getScalable() : SOffset.getFixed(); in isAArch64FrameOffsetLegal()
4345 SOffset = StackOffset::get(SOffset.getFixed(), Offset); in isAArch64FrameOffsetLegal()
4347 SOffset = StackOffset::get(Offset, SOffset.getScalable()); in isAArch64FrameOffsetLegal()
4349 (SOffset ? 0 : AArch64FrameOffsetIsLegal); in isAArch64FrameOffsetLegal()