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Searched refs:SOP2 (Results 1 – 13 of 13) sorted by relevance

/netbsd-src/external/gpl3/binutils.old/dist/include/opcode/
H A Darc.h483 #define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F)) argument
/netbsd-src/external/gpl3/binutils/dist/include/opcode/
H A Darc.h483 #define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F)) argument
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIInstrFormats.td22 field bit SOP2 = 0;
149 let TSFlags{3} = SOP2;
H A DSOPInstructions.td340 // SOP2 Instructions
351 let SOP2 = 1;
1370 // SOP2 Patterns
1531 // SOP2 - GFX10.
1550 // SOP2 - GFX6, GFX7.
1979 // SOP2 - GFX9.
H A DSIInstrInfo.h372 return MI.getDesc().TSFlags & SIInstrFlags::SOP2; in isSOP2()
376 return get(Opcode).TSFlags & SIInstrFlags::SOP2; in isSOP2()
H A DSIDefines.h26 SOP2 = 1 << 3, enumerator
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp3901 if (!(Desc.TSFlags & (SIInstrFlags::SOP2 | SIInstrFlags::SOPC))) in validateSOPLiteral()
/netbsd-src/external/apache2/llvm/dist/llvm/docs/AMDGPU/
H A DAMDGPUAsmGFX7.rst498 SOP2 section in Instructions
H A DAMDGPUAsmGFX8.rst520 SOP2 section in Instructions
H A DAMDGPUAsmGFX9.rst683 SOP2 section in Instructions
H A DAMDGPUAsmGFX90a.rst595 SOP2 section in Instructions
H A DAMDGPUAsmGFX10.rst1162 SOP2 section in Instructions
/netbsd-src/external/apache2/llvm/dist/llvm/docs/
H A DAMDGPUUsage.rst11505 SOP2 subsubsection
11520 For full list of supported instructions, refer to "SOP2 Instructions" in ISA