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Searched refs:SF (Results 1 – 25 of 478) sorted by relevance

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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
H A Ddcn20_mmhubbub.h57 #define SF(reg_name, field_name, post_fix)\ macro
120 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
121 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
122 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
123 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
124 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
125 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
126 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
127 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
128 SF(MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB_BUFMGR_CUR_LINE_R, mask_sh),\
[all …]
H A Ddcn20_dwb.h55 #define SF(reg_name, field_name, post_fix)\ macro
108 SF(WB_ENABLE, WB_ENABLE, mask_sh),\
109 SF(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
110 SF(WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
111 SF(WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
112 SF(WB_EC_CONFIG, WB_TEST_CLK_SEL, mask_sh),\
113 SF(WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
114 SF(WB_EC_CONFIG, WB_LB_SD_DIS, mask_sh),\
115 SF(WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
116 SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_MODE_SEL, mask_sh),\
[all …]
H A Ddcn20_optc.h50 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_X, mask_sh),\
51 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_Y, mask_sh),\
52 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
53 SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
54 SF(OTG0_OTG_GLOBAL_CONTROL2, DIG_UPDATE_LOCATION, mask_sh),\
55 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\
56 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
57 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
58 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
59 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
[all …]
H A Ddcn20_mpc.h140 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
141 SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
142 SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
143 SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
144 SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
145 SF(MPC_OCSC_TEST_DEBUG_INDEX, MPC_OCSC_TEST_DEBUG_INDEX, mask_sh),\
146 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
147 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
148 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
149 SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
[all …]
H A Ddcn20_vmid.h43 #define SF(reg_name, field_name, post_fix)\ macro
56 SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_DEPTH, mask_sh),\
57 SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE, mask_sh),\
58 SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
59 SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
60 …SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4, mask_sh)…
61 …SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32, mask_sh…
62 SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
63 SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32, mask_sh)
/netbsd-src/external/gpl3/gdb.old/dist/sim/common/
H A Dcgen-fpu.h13 typedef USI SF; typedef
68 SF (*addsf) (CGEN_FPU*, SF, SF);
69 SF (*subsf) (CGEN_FPU*, SF, SF);
70 SF (*mulsf) (CGEN_FPU*, SF, SF);
71 SF (*divsf) (CGEN_FPU*, SF, SF);
72 SF (*remsf) (CGEN_FPU*, SF, SF);
73 SF (*negsf) (CGEN_FPU*, SF);
74 SF (*abssf) (CGEN_FPU*, SF);
75 SF (*sqrtsf) (CGEN_FPU*, SF);
76 SF (*invsf) (CGEN_FPU*, SF);
[all …]
/netbsd-src/external/gpl3/gdb/dist/sim/common/
H A Dcgen-fpu.h13 typedef USI SF; typedef
68 SF (*addsf) (CGEN_FPU*, SF, SF);
69 SF (*subsf) (CGEN_FPU*, SF, SF);
70 SF (*mulsf) (CGEN_FPU*, SF, SF);
71 SF (*divsf) (CGEN_FPU*, SF, SF);
72 SF (*remsf) (CGEN_FPU*, SF, SF);
73 SF (*negsf) (CGEN_FPU*, SF);
74 SF (*abssf) (CGEN_FPU*, SF);
75 SF (*sqrtsf) (CGEN_FPU*, SF);
76 SF (*invsf) (CGEN_FPU*, SF);
[all …]
H A Dcgen-accfp.c22 static SF
23 addsf (CGEN_FPU* fpu, SF x, SF y) in addsf()
41 static SF
42 subsf (CGEN_FPU* fpu, SF x, SF y) in subsf()
60 static SF
61 mulsf (CGEN_FPU* fpu, SF x, SF y) in mulsf()
79 static SF
80 divsf (CGEN_FPU* fpu, SF x, SF y) in divsf()
98 static SF
99 remsf (CGEN_FPU* fpu, SF x, SF y) in remsf()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
H A Ddcn10_optc.h178 SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
179 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
180 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
181 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
182 SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, mask_sh),\
183 SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DE_MODE, mask_sh),\
184 SF(OTG0_OTG_BLANK_CONTROL, OTG_CURRENT_BLANK_STATE, mask_sh),\
185 SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
186 SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
187 SF(OTG0_OTG_GLOBAL_CONTROL0, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
[all …]
H A Ddcn10_dwb.h51 #define SF(reg_name, field_name, post_fix)\ macro
89 SF(CNV0_WB_ENABLE, WB_ENABLE, mask_sh),\
90 SF(CNV0_WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
91 SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
92 SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
93 SF(CNV0_WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
94 SF(CNV0_WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
95 SF(CNV0_CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
96 SF(CNV0_CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
97 SF(CNV0_CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\
[all …]
H A Ddcn10_mpc.h63 SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\
64 SF(MPCC0_MPCC_BOT_SEL, MPCC_BOT_SEL, mask_sh),\
65 SF(MPCC0_MPCC_CONTROL, MPCC_MODE, mask_sh),\
66 SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_BLND_MODE, mask_sh),\
67 SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_MULTIPLIED_MODE, mask_sh),\
68 SF(MPCC0_MPCC_CONTROL, MPCC_BLND_ACTIVE_OVERLAP_ONLY, mask_sh),\
69 SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_ALPHA, mask_sh),\
70 SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_GAIN, mask_sh),\
71 SF(MPCC0_MPCC_STATUS, MPCC_IDLE, mask_sh),\
72 SF(MPCC0_MPCC_STATUS, MPCC_BUSY, mask_sh),\
[all …]
/netbsd-src/external/gpl3/gcc/dist/gcc/config/csky/
H A Dcsky_insn_fpuv2.md26 [(set (match_operand:SF 0 "register_operand" "=v,a,r")
27 (abs:SF (match_operand:SF 1 "register_operand" "v, 0,r")))]
47 [(set (match_operand:SF 0 "register_operand" "=v")
48 (neg:SF (match_operand:SF 1 "register_operand" "v")))]
64 [(set (match_operand:SF 0 "register_operand" "=v")
65 (sqrt:SF (match_operand:SF 1 "register_operand" "v")))]
81 [(set (match_operand:SF 0 "register_operand" "=v")
82 (plus:SF (match_operand:SF 1 "register_operand" "v")
83 (match_operand:SF 2 "register_operand" "v")))]
100 [(set (match_operand:SF 0 "register_operand" "=v")
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/csky/
H A Dcsky_insn_fpu.md26 [(set (match_operand:SF 0 "register_operand" "=v,r")
27 (abs:SF (match_operand:SF 1 "register_operand" "v, r")))]
45 [(set (match_operand:SF 0 "register_operand" "=v")
46 (neg:SF (match_operand:SF 1 "register_operand" "v")))]
62 [(set (match_operand:SF 0 "register_operand" "=v")
63 (sqrt:SF (match_operand:SF 1 "register_operand" "v")))]
79 [(set (match_operand:SF 0 "register_operand" "=v")
80 (plus:SF (match_operand:SF 1 "register_operand" "v")
81 (match_operand:SF 2 "register_operand" "v")))]
98 [(set (match_operand:SF 0 "register_operand" "=v")
[all …]
/netbsd-src/external/bsd/pcc/dist/pcc/mip/
H A Dsoftfloat.h44 typedef struct softfloat SF; typedef
45 SF soft_neg(SF);
46 SF soft_cast(CONSZ v, TWORD);
47 SF soft_plus(SF, SF);
48 SF soft_minus(SF, SF);
49 SF soft_mul(SF, SF);
50 SF soft_div(SF, SF);
51 int soft_cmp_eq(SF, SF);
52 int soft_cmp_ne(SF, SF);
53 int soft_cmp_ge(SF, SF);
[all …]
/netbsd-src/external/mit/isl/dist/
H A Disl_map_lexopt_templ.c18 #define SF(TYPE,SUFFIX) xSF(TYPE,SUFFIX) macro
31 static __isl_give TYPE *SF(isl_basic_map_partial_lexopt,SUFFIX)( in SF() function
35 return SF(isl_tab_basic_map_partial_lexopt,SUFFIX)(bmap, dom, empty, in SF()
39 __isl_give TYPE *SF(isl_basic_map_partial_lexmax,SUFFIX)( in SF() function
44 return SF(isl_basic_map_partial_lexopt,SUFFIX)(bmap, dom, empty, flags); in SF()
47 __isl_give TYPE *SF(isl_basic_map_partial_lexmin,SUFFIX)( in SF() function
52 return SF(isl_basic_map_partial_lexopt,SUFFIX)(bmap, dom, empty, flags); in SF()
55 __isl_give TYPE *SF(isl_basic_set_partial_lexmin,SUFFIX)( in SF() function
59 return SF(isl_basic_map_partial_lexmin,SUFFIX)(bset, dom, empty); in SF()
62 __isl_give TYPE *SF(isl_basic_set_partial_lexmax,SUFFIX)( in SF() function
[all …]
/netbsd-src/external/bsd/pcc/dist/pcc/cc/cxxcom/
H A Dsoftfloat.c66 static SF
69 SF rv; in nulldf()
79 SF
83 SF rv; in soft_cast()
103 SF
104 soft_mul(SF p1, SF p2) in soft_mul()
106 SF rv; in soft_mul()
149 SF
150 soft_div(SF t, SF n) in soft_div()
152 SF rv; in soft_div()
[all …]
/netbsd-src/external/bsd/pcc/dist/pcc/cc/ccom/
H A Dsoftfloat.c66 static SF
69 SF rv; in nulldf()
79 SF
83 SF rv; in soft_cast()
103 SF
104 soft_mul(SF p1, SF p2) in soft_mul()
106 SF rv; in soft_mul()
149 SF
150 soft_div(SF t, SF n) in soft_div()
152 SF rv; in soft_div()
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/arc/
H A Dfpu.md9 [(set (match_operand:SF 0 "register_operand" "=r,r, r,r,r,r")
10 (plus:SF (match_operand:SF 1 "nonmemory_operand" "%0,r, r,0,r,F")
11 (match_operand:SF 2 "nonmemory_operand" "r,r,CfZ,F,F,r")))]
25 [(set (match_operand:SF 0 "register_operand" "=r,r, r,r,r,r")
26 (minus:SF (match_operand:SF 1 "nonmemory_operand" "0,r, r,0,r,F")
27 (match_operand:SF 2 "nonmemory_operand" "r,r,CfZ,F,F,r")))]
41 [(set (match_operand:SF 0 "register_operand" "=r,r,r,r,r")
42 (mult:SF (match_operand:SF 1 "nonmemory_operand" "%0,r,0,r,F")
43 (match_operand:SF 2 "nonmemory_operand" "r,r,F,F,r")))]
57 [(set (match_operand:SF 0 "register_operand" "")
[all …]
/netbsd-src/external/gpl3/gcc/dist/gcc/config/arc/
H A Dfpu.md9 [(set (match_operand:SF 0 "register_operand" "=r,r, r,r,r,r")
10 (plus:SF (match_operand:SF 1 "nonmemory_operand" "%0,r, r,0,r,F")
11 (match_operand:SF 2 "nonmemory_operand" "r,r,CfZ,F,F,r")))]
25 [(set (match_operand:SF 0 "register_operand" "=r,r, r,r,r,r")
26 (minus:SF (match_operand:SF 1 "nonmemory_operand" "0,r, r,0,r,F")
27 (match_operand:SF 2 "nonmemory_operand" "r,r,CfZ,F,F,r")))]
41 [(set (match_operand:SF 0 "register_operand" "=r,r,r,r,r")
42 (mult:SF (match_operand:SF 1 "nonmemory_operand" "%0,r,0,r,F")
43 (match_operand:SF 2 "nonmemory_operand" "r,r,F,F,r")))]
57 [(set (match_operand:SF 0 "register_operand" "")
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp41 static void SetValue(Value *V, GenericValue Val, ExecutionContext &SF) { in SetValue() argument
42 SF.Values[V] = Val; in SetValue()
63 ExecutionContext &SF = ECStack.back(); in visitUnaryOperator() local
65 GenericValue Src = getOperandValue(I.getOperand(0), SF); in visitUnaryOperator()
96 SetValue(&I, R, SF); in visitUnaryOperator()
333 ExecutionContext &SF = ECStack.back(); in visitICmpInst() local
335 GenericValue Src1 = getOperandValue(I.getOperand(0), SF); in visitICmpInst()
336 GenericValue Src2 = getOperandValue(I.getOperand(1), SF); in visitICmpInst()
355 SetValue(&I, R, SF); in visitICmpInst()
666 ExecutionContext &SF = ECStack.back(); in visitFCmpInst() local
[all …]
H A DInterpreter.h189 gep_type_iterator E, ExecutionContext &SF);
195 void SwitchToNewBasicBlock(BasicBlock *Dest, ExecutionContext &SF);
201 GenericValue getConstantExprValue(ConstantExpr *CE, ExecutionContext &SF);
202 GenericValue getOperandValue(Value *V, ExecutionContext &SF);
204 ExecutionContext &SF);
206 ExecutionContext &SF);
208 ExecutionContext &SF);
210 ExecutionContext &SF);
212 ExecutionContext &SF);
214 ExecutionContext &SF);
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
H A Ddce_audio.h46 #define SF(reg_name, field_name, post_fix)\ macro
51 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
52 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
53 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO2_USE_512FBR_DTO, mask_sh),\
54 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_USE_512FBR_DTO, mask_sh),\
55 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO1_USE_512FBR_DTO, mask_sh),\
56 SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
57 SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
58 SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\
59 SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/rs6000/
H A Dpaired.md99 (fma:SF
100 (vec_select:SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
102 (vec_select:SF (match_operand:V2SF 2 "gpc_reg_operand" "f")
104 (vec_select:SF (match_operand:V2SF 3 "gpc_reg_operand" "f")
106 (fma:SF
107 (vec_select:SF (match_dup 1)
109 (vec_select:SF (match_dup 2)
111 (vec_select:SF (match_dup 3)
120 (fma:SF
121 (vec_select:SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DSubtargetFeatureInfo.cpp56 for (const auto &SF : SubtargetFeatures) { in emitSubtargetFeatureBitEnumeration() local
57 const SubtargetFeatureInfo &SFI = SF.second; in emitSubtargetFeatureBitEnumeration()
69 for (const auto &SF : SubtargetFeatures) in emitNameTable() local
70 if (IndexUB <= SF.second.Index) in emitNameTable()
71 IndexUB = SF.second.Index+1; in emitNameTable()
76 for (const auto &SF : SubtargetFeatures) in emitNameTable() local
77 Names[SF.second.Index] = SF.second.getEnumName(); in emitNameTable()
99 for (const auto &SF : SubtargetFeatures) { in emitComputeAvailableFeatures() local
100 const SubtargetFeatureInfo &SFI = SF.second; in emitComputeAvailableFeatures()
117 for (const auto &SF : SubtargetFeatures) { in emitComputeAssemblerAvailableFeatures() local
[all …]
/netbsd-src/external/gpl3/gcc/dist/gcc/config/h8300/
H A Dother.md6 [(set (match_operand:SF 0 "register_operand" "=r")
7 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
11 [(parallel [(set (match_dup 0) (abs:SF (match_dup 1)))
15 [(set (match_operand:SF 0 "register_operand" "=r")
16 (abs:SF (match_operand:SF 1 "register_operand" "0")))

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