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Searched refs:SETULT (Results 1 – 25 of 50) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1355 SETULT, // 1 1 0 0 True if unordered or less than enumerator
1381 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEISelDAGToDAG.cpp43 case ISD::SETULT: in intCondCode2Icc()
87 case ISD::SETULT: in fpCondCode2Fcc()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DAnalysis.cpp204 case FCmpInst::FCMP_ULT: return ISD::SETULT; in getFCmpCondCode()
216 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
236 case ICmpInst::ICMP_ULT: return ISD::SETULT; in getICmpCondCode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3301 case ISD::SETULT: { in get32BitZExtCompare()
3474 case ISD::SETULT: { in get32BitSExtCompare()
3630 case ISD::SETULT: { in get64BitZExtCompare()
3793 case ISD::SETULT: { in get64BitSExtCompare()
4048 case ISD::SETULT: in SelectCC()
4075 case ISD::SETULT: in SelectCC()
4136 case ISD::SETULT: return PPC::PRED_LT; in getPredicateForSetCC()
4168 case ISD::SETULT: return 0; in getCRIdxForSetCC()
4190 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break; in getVCmpInst()
4198 case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break; in getVCmpInst()
[all …]
H A DPPCInstrInfo.td3693 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
3756 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
3936 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
3964 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
3976 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
4004 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
4199 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)),
4230 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)),
4251 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)),
4273 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
[all …]
H A DPPCInstrSPE.td840 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
861 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)),
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td77 defm LT_U : ComparisonInt<SETULT, "lt_u", 0x49, 0x54>;
H A DWebAssemblyISelLowering.cpp105 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE}) in WebAssemblyTargetLowering()
216 for (auto CC : {ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE}) in WebAssemblyTargetLowering()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp581 case ISD::SETULT: in NegateCC()
793 SET_NEWCC(SETULT, JULT); in EmitInstrWithCustomInserter()
H A DBPFInstrInfo.td101 [{return (N->getZExtValue() == ISD::SETULT);}]>;
121 [{return (N->getZExtValue() == ISD::SETULT);}]>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp380 case ISD::SETULT: in softenSetCCOperands()
3235 if (Cond == ISD::CondCode::SETULT) { in optimizeSetCCOfSignedTruncationCheck()
3436 if (Cond == ISD::SETULT || Cond == ISD::SETUGT) { in simplifySetCCWithCTPOP()
3438 if (C1.ugt(CostLimit + (Cond == ISD::SETULT))) in simplifySetCCWithCTPOP()
3440 if (C1 == 0 && (Cond == ISD::SETULT)) in simplifySetCCWithCTPOP()
3443 unsigned Passes = C1.getLimitedValue() - (Cond == ISD::SETULT); in simplifySetCCWithCTPOP()
3451 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in simplifySetCCWithCTPOP()
3713 case ISD::SETULT: in SimplifySetCC()
3736 case ISD::SETULT: in SimplifySetCC()
3929 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; in SimplifySetCC()
[all …]
H A DLegalizeIntegerTypes.cpp1621 case ISD::SETULT: in PromoteSetCCOperands()
2444 Amt, NVBitsNode, ISD::SETULT); in ExpandShiftWithUnknownAmountBit()
2514 return std::make_pair(ISD::SETULT, ISD::UMIN); in getExpandedMinMaxOps()
2644 ISD::SETULT); in ExpandIntRes_ADDSUB()
2656 ISD::SETULT); in ExpandIntRes_ADDSUB()
2665 LoOps[0], LoOps[1], ISD::SETULT); in ExpandIntRes_ADDSUB()
2738 Cond = ISD::SETULT; in ExpandIntRes_UADDSUBO()
3573 SDValue HLULT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLHiMask, ISD::SETULT); in ExpandIntRes_MULFIX()
4280 case ISD::SETULT: LowCC = ISD::SETULT; break; in IntegerExpandSetCCOperands()
4350 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break; in IntegerExpandSetCCOperands()
H A DSelectionDAGDumper.cpp450 case ISD::SETULT: return "setult"; in getOperationName()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVVLPatterns.td688 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>;
695 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>;
699 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>;
709 defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSLEU", SETULT,
H A DRISCVInstrInfoVSDPatterns.td437 defm : VPatIntegerSetCCSDNode_VV_VX<SETULT, "PseudoVMSLTU">;
440 defm : VPatIntegerSetCCSDNode_VIPlus1<SETULT, "PseudoVMSLEU",
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp48 case ISD::SETULT: in ISDCCtoARCCC()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructions.td285 def COND_ULT : PatFrag<(ops), (OtherVT SETULT)>;
H A DR600ISelLowering.cpp108 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); in R600TargetLowering()
114 setCondCodeAction(ISD::SETULT, MVT::i32, Expand); in R600TargetLowering()
H A DSIWholeQuadMode.cpp812 case ISD::SETULT: in lowerKillF32()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp960 case ISD::SETULT: in isLegalDSPCondCode()
1766 Op->getOperand(2), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
1772 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
1855 Op->getOperand(2), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
H A DMipsMSAInstrInfo.td150 def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>;
151 def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>;
178 def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>;
179 def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>;
180 def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>;
181 def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>;
H A DMipsDSPInstrInfo.td1428 def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1441 def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp509 case ISD::SETULT: in intCCToAVRCC()
633 CC = ISD::SETULT; in getAVRCmp()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1497 case ISD::SETULT: in TranslateIntegerM68kCC()
1575 case ISD::SETULT: in TranslateM68kCC()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td729 def SETULT : CondCode<"FCMP_ULT", "ICMP_ULT">;
1336 (setcc node:$lhs, node:$rhs, SETULT)>;

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