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Searched refs:SETLT (Results 1 – 25 of 52) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1364 SETLT, // 1 X 1 0 0 True if less than enumerator
1375 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; in isSignedIntSetCC()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEISelDAGToDAG.cpp35 case ISD::SETLT: in intCondCode2Icc()
67 case ISD::SETLT: in fpCondCode2Fcc()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp583 case ISD::SETLT: in NegateCC()
792 SET_NEWCC(SETLT, JSLT); in EmitInstrWithCustomInserter()
803 CC == ISD::SETLT || in EmitInstrWithCustomInserter()
H A DBPFInstrInfo.td99 [{return (N->getZExtValue() == ISD::SETLT);}]>;
119 [{return (N->getZExtValue() == ISD::SETLT);}]>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DAnalysis.cpp216 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
235 case ICmpInst::ICMP_SLT: return ISD::SETLT; in getICmpCondCode()
H A DTargetLoweringBase.cpp653 CCs[RTLIB::OLT_F32] = ISD::SETLT; in InitCmpLibcallCCs()
654 CCs[RTLIB::OLT_F64] = ISD::SETLT; in InitCmpLibcallCCs()
655 CCs[RTLIB::OLT_F128] = ISD::SETLT; in InitCmpLibcallCCs()
656 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT; in InitCmpLibcallCCs()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3247 case ISD::SETLT: { in get32BitZExtCompare()
3426 case ISD::SETLT: { in get32BitSExtCompare()
3581 case ISD::SETLT: { in get64BitZExtCompare()
3741 case ISD::SETLT: { in get64BitSExtCompare()
4044 case ISD::SETLT: in SelectCC()
4071 case ISD::SETLT: in SelectCC()
4122 case ISD::SETLT: in getPredicateForSetCC()
4149 case ISD::SETLT: return 0; // Bit #0 = SETOLT in getCRIdxForSetCC()
4186 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break; in getVCmpInst()
4232 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break; in getVCmpInst()
[all …]
H A DPPCInstrInfo.td3691 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
3831 defm : ExtSetCCPat<SETLT,
3863 defm : ExtSetCCPat<SETLT,
3938 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
3966 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
3978 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
4006 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
4093 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLT)),
4137 def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETLT)),
4164 def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETLT)),
[all …]
H A DPPCInstrSPE.td838 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
859 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp338 case ISD::SETLT: in softenSetCCOperands()
786 if (CC == ISD::SETLT && Op1.getValueType().isInteger() && in SimplifyMultipleUseDemandedBits()
1428 if (CC == ISD::SETLT && Op1.getValueType().isInteger() && in SimplifyDemandedBits()
3721 case ISD::SETLT: in SimplifySetCC()
3929 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; in SimplifySetCC()
3941 if (Cond == ISD::SETLT || Cond == ISD::SETULT) { in SimplifySetCC()
4056 ISD::SETLT); in SimplifySetCC()
4346 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X in SimplifySetCC()
5974 return DAG.getSetCC(DL, CCVT, Fabs, NormC, ISD::SETLT); in getSqrtInputTest()
6422 Next = DAG.getSelectCC(dl, LH, Zero, NextSub, Next, ISD::SETLT); in expandMUL_LOHI()
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H A DLegalizeIntegerTypes.cpp1627 case ISD::SETLT: in PromoteSetCCOperands()
2512 return std::make_pair(ISD::SETLT, ISD::UMIN); in getExpandedMinMaxOps()
3430 SDValue ProdNeg = DAG.getSetCC(dl, BoolVT, Product, Zero, ISD::SETLT); in ExpandIntRes_MULFIX()
3571 SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT); in ExpandIntRes_MULFIX()
3580 SDValue HLNeg = DAG.getSetCC(dl, BoolNVT, ResultHL, NVTZero, ISD::SETLT); in ExpandIntRes_MULFIX()
3584 SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT); in ExpandIntRes_MULFIX()
3598 SatMin = DAG.getSetCC(dl, BoolNVT, ResultHH, HHHiMask, ISD::SETLT); in ExpandIntRes_MULFIX()
3693 Ovf = DAG.getSetCC(dl, OType, Ovf, DAG.getConstant(0, dl, VT), ISD::SETLT); in ExpandIntRes_SADDSUBO()
4268 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 in IntegerExpandSetCCOperands()
4279 case ISD::SETLT: in IntegerExpandSetCCOperands()
[all …]
H A DSelectionDAGDumper.cpp457 case ISD::SETLT: return "setlt"; in getOperationName()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVVLPatterns.td687 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>;
694 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>;
698 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>;
707 defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSLE", SETLT,
924 defm : VPatFPSetCCVL_VV_VF_FV<SETLT, "PseudoVMFLT", "PseudoVMFGT">;
H A DRISCVInstrInfoVSDPatterns.td436 defm : VPatIntegerSetCCSDNode_VV_VX<SETLT, "PseudoVMSLT">;
438 defm : VPatIntegerSetCCSDNode_VIPlus1<SETLT, "PseudoVMSLE",
651 defm : VPatFPSetCCSDNode_VV_VF_FV<SETLT, "PseudoVMFLT", "PseudoVMFGT">;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td76 defm LT_S : ComparisonInt<SETLT, "lt_s", 0x48, 0x53>;
H A DWebAssemblyInstrSIMD.td665 defm LT_S : SIMDConditionInt<"lt_s", SETLT, 37>;
666 defm LT_S : SIMDCondition<I64x2, "lt_s", SETLT, 216>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h1008 X86_INTRINSIC_DATA(sse_comilt_ss, COMI, X86ISD::COMI, ISD::SETLT),
1025 X86_INTRINSIC_DATA(sse_ucomilt_ss, COMI, X86ISD::UCOMI, ISD::SETLT),
1033 X86_INTRINSIC_DATA(sse2_comilt_sd, COMI, X86ISD::COMI, ISD::SETLT),
1080 X86_INTRINSIC_DATA(sse2_ucomilt_sd, COMI, X86ISD::UCOMI, ISD::SETLT),
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructions.td272 def COND_OLT : PatFrags<(ops), [(OtherVT SETOLT), (OtherVT SETLT)]>;
298 def COND_SLT : PatFrag<(ops), (OtherVT SETLT)>;
H A DAMDGPUISelLowering.cpp1413 case ISD::SETLT: { in combineFMinMaxLegacy()
2070 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT); in LowerSDIVREM()
2071 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT); in LowerSDIVREM()
2192 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT); in LowerFTRUNC()
2685 SDValue V = DAG.getSelectCC(DL, E, One, D, N, ISD::SETLT); in LowerFP_TO_FP16()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp505 case ISD::SETLT: in intCCToAVRCC()
577 CC = ISD::SETLT; in getAVRCmp()
592 CC = ISD::SETLT; in getAVRCmp()
595 case ISD::SETLT: { in getAVRCmp()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp202 { RTLIB::OLT_F64, "__mspabi_cmpd", ISD::SETLT }, in MSP430TargetLowering()
208 { RTLIB::OLT_F32, "__mspabi_cmpf", ISD::SETLT }, in MSP430TargetLowering()
1108 case ISD::SETLT: in EmitCMP()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1491 case ISD::SETLT: in TranslateIntegerM68kCC()
1521 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { in TranslateM68kCC()
1525 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { in TranslateM68kCC()
1576 case ISD::SETLT: in TranslateM68kCC()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp60 case ISD::SETLT: in ISDCCtoARCCC()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsMSAInstrInfo.td122 def vfsetlt_v4f32 : vfsetcc_type<v4i32, v4f32, SETLT>;
123 def vfsetlt_v2f64 : vfsetcc_type<v2i64, v2f64, SETLT>;
170 def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>;
171 def vsetlt_v8i16 : vsetcc_type<v8i16, SETLT>;
172 def vsetlt_v4i32 : vsetcc_type<v4i32, SETLT>;
173 def vsetlt_v2i64 : vsetcc_type<v2i64, SETLT>;
H A DMipsDSPInstrInfo.td1422 def : DSPSetCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1435 def : DSPSelectCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;

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