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Searched refs:SETCC (Results 1 – 25 of 61) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp127 setOperationAction(ISD::SETCC, VT, Custom); in M68kTargetLowering()
1327 case ISD::SETCC: in LowerOperation()
1402 SDValue SetCC = DAG.getNode(M68kISD::SETCC, DL, N->getValueType(1), in LowerXALUO()
1428 return DAG.getNode(M68kISD::SETCC, DL, MVT::i8, in getBitTestCondition()
1618 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC && in hasNonFlagsUse()
1930 if (Op0.getOpcode() == M68kISD::SETCC) { in LowerSETCC()
1938 DAG.getNode(M68kISD::SETCC, DL, MVT::i8, in LowerSETCC()
1962 return DAG.getNode(M68kISD::SETCC, DL, MVT::i8, in LowerSETCC()
1986 return DAG.getNode(M68kISD::SETCC, DL, MVT::i8, in LowerSETCCCARRY()
2026 if (Cond.getOpcode() == ISD::SETCC) { in LowerSELECT()
[all …]
H A DM68kInstrInfo.h185 static inline bool IsSETCC(unsigned SETCC) { in IsSETCC() argument
186 switch (SETCC) { in IsSETCC()
H A DM68kISelLowering.h53 SETCC, enumerator
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2220 { ISD::SETCC, MVT::v2i64, 2 }, in getCmpSelInstrCost()
2224 { ISD::SETCC, MVT::v32i16, 1 }, in getCmpSelInstrCost()
2225 { ISD::SETCC, MVT::v64i8, 1 }, in getCmpSelInstrCost()
2232 { ISD::SETCC, MVT::v8i64, 1 }, in getCmpSelInstrCost()
2233 { ISD::SETCC, MVT::v16i32, 1 }, in getCmpSelInstrCost()
2234 { ISD::SETCC, MVT::v8f64, 1 }, in getCmpSelInstrCost()
2235 { ISD::SETCC, MVT::v16f32, 1 }, in getCmpSelInstrCost()
2242 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 in getCmpSelInstrCost()
2243 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 in getCmpSelInstrCost()
2250 { ISD::SETCC, MVT::v4i64, 1 }, in getCmpSelInstrCost()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.h41 SETCC, enumerator
H A DLanaiISelLowering.cpp88 setOperationAction(ISD::SETCC, MVT::i32, Custom); in LanaiTargetLowering()
192 case ISD::SETCC: in LowerOperation()
980 return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag); in LowerSETCC()
1104 case LanaiISD::SETCC: in getTargetNodeName()
1495 case LanaiISD::SETCC: in computeKnownBitsForTargetNode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h54 SETCC, enumerator
H A DMSP430ISelLowering.cpp92 setOperationAction(ISD::SETCC, MVT::i8, Custom); in MSP430TargetLowering()
93 setOperationAction(ISD::SETCC, MVT::i16, Custom); in MSP430TargetLowering()
347 case ISD::SETCC: return LowerSETCC(Op, DAG); in LowerOperation()
1380 case MSP430ISD::SETCC: return "MSP430ISD::SETCC"; in getTargetNodeName()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/IR/
H A DConstrainedOps.def65 // Both of these match to FCmp / SETCC.
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp183 setOperationAction(ISD::SETCC, T, Custom); in initializeHVXLowering()
212 setOperationAction(ISD::SETCC, BoolW, Custom); in initializeHVXLowering()
256 setOperationAction(ISD::SETCC, VecTy, Custom); in initializeHVXLowering()
264 setOperationAction(ISD::SETCC, BoolTy, Custom); in initializeHVXLowering()
1964 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, ResTy, in WidenHvxSetCC()
2087 case ISD::SETCC: in LowerHvxOperation()
2118 case ISD::SETCC: in LowerHvxOperation()
2147 case ISD::SETCC: in LowerHvxOperationWrapper()
2199 case ISD::SETCC: in ReplaceHvxNodeResults()
H A DHexagonISelLowering.cpp1519 setOperationAction(ISD::SETCC, MVT::i8, Custom); in HexagonTargetLowering()
1520 setOperationAction(ISD::SETCC, MVT::i16, Custom); in HexagonTargetLowering()
1521 setOperationAction(ISD::SETCC, MVT::v4i8, Custom); in HexagonTargetLowering()
1522 setOperationAction(ISD::SETCC, MVT::v2i16, Custom); in HexagonTargetLowering()
1748 setOperationAction(ISD::SETCC, MVT::v2i16, Custom); in HexagonTargetLowering()
3168 case ISD::SETCC: return LowerSETCC(Op, DAG); in LowerOperation()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h692 SETCC, enumerator
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break; in ScalarizeVectorResult()
467 if (Cond->getOpcode() == ISD::SETCC) { in ScalarizeVecRes_VSELECT()
575 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, in ScalarizeVecRes_SETCC()
631 case ISD::SETCC: in ScalarizeVectorOperand()
776 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, in ScalarizeVecOp_VSETCC()
944 case ISD::SETCC: in SplitVectorResult()
1746 if (Mask.getOpcode() == ISD::SETCC) { in SplitVecRes_MLOAD()
1831 if (Mask.getOpcode() == ISD::SETCC) { in SplitVecRes_MGATHER()
2154 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break; in SplitVectorOperand()
2593 if (OpNo == 1 && Mask.getOpcode() == ISD::SETCC) { in SplitVecOp_MSTORE()
[all …]
H A DLegalizeVectorOps.cpp498 case ISD::SETCC: { in LegalizeOp()
772 case ISD::SETCC: in Expand()
1373 LHS = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), LHS, RHS, CC, in ExpandSETCC()
1529 Ops[i] = DAG.getNode(ISD::SETCC, dl, in UnrollVSETCC()
H A DLegalizeDAG.cpp1036 case ISD::SETCC: in LegalizeOp()
1041 Node->getOpcode() == ISD::SETCC ? 2 : 1; in LegalizeOp()
3490 if (Tmp1.getOpcode() == ISD::SETCC) { in ExpandNode()
3549 if (Tmp2.getOpcode() == ISD::SETCC) { in ExpandNode()
3571 case ISD::SETCC: in ExpandNode()
3574 bool IsStrict = Node->getOpcode() != ISD::SETCC; in ExpandNode()
3589 Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), in ExpandNode()
3648 SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC, Node->getFlags()); in ExpandNode()
4377 Node->getOpcode() == ISD::SETCC || in PromoteNode()
4629 case ISD::SETCC: in PromoteNode()
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H A DDAGCombiner.cpp894 if (N.getOpcode() == ISD::SETCC) { in isSetCCEquivalent()
1667 case ISD::SETCC: return visitSETCC(N); in visit()
2183 if (Z.getOperand(0).getOpcode() != ISD::SETCC || in foldAddSubBoolOfMaskedVal()
5085 TLI.isOperationLegal(ISD::SETCC, OpVT)))) in foldLogicOfSetCCs()
7771 case ISD::SETCC: in visitXOR()
8199 if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC && in visitSHL()
9231 if (Cond.getOpcode() != ISD::SETCC || !Cond.hasOneUse() || in foldSelectOfConstantsUsingSra()
9508 if (N0.getOpcode() == ISD::SETCC) { in visitSELECT()
9866 if (N0.getOpcode() == ISD::SETCC) { in visitVSELECT()
9921 TLI.isOperationLegalOrCustom(ISD::SETCC, WideVT)) { in visitVSELECT()
[all …]
H A DLegalizeFloatTypes.cpp836 case ISD::SETCC: Res = SoftenFloatOp_SETCC(N); break; in SoftenFloatOperand()
1017 NewLHS = DAG.getNode(ISD::SETCC, SDLoc(N), N->getValueType(0), NewLHS, in SoftenFloatOp_SETCC()
1782 case ISD::SETCC: Res = ExpandFloatOp_SETCC(N); break; in ExpandFloatOperand()
2089 case ISD::SETCC: R = PromoteFloatOp_SETCC(N, OpNo); break; in PromoteFloatOperand()
2886 case ISD::SETCC: Res = SoftPromoteHalfOp_SETCC(N); break; in SoftPromoteHalfOperand()
H A DLegalizeTypesGeneric.cpp527 else if (Cond.getOpcode() == ISD::SETCC) { in SplitRes_SELECT()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp107 setOperationAction(ISD::SETCC, MVT::i8, Custom); in AVRTargetLowering()
108 setOperationAction(ISD::SETCC, MVT::i16, Custom); in AVRTargetLowering()
109 setOperationAction(ISD::SETCC, MVT::i32, Custom); in AVRTargetLowering()
110 setOperationAction(ISD::SETCC, MVT::i64, Custom); in AVRTargetLowering()
804 case ISD::SETCC: in LowerOperation()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp119 setOperationAction(ISD::SETCC, MVT::v4i32, Expand); in R600TargetLowering()
120 setOperationAction(ISD::SETCC, MVT::v2i32, Expand); in R600TargetLowering()
136 setOperationAction(ISD::SETCC, MVT::i32, Expand); in R600TargetLowering()
137 setOperationAction(ISD::SETCC, MVT::f32, Expand); in R600TargetLowering()
796 ISD::SETCC, in lowerFP_TO_UINT()
806 ISD::SETCC, in lowerFP_TO_SINT()
H A DAMDGPUISelLowering.h369 SETCC, enumerator
H A DSIISelLowering.cpp198 setOperationAction(ISD::SETCC, MVT::i1, Promote); in SITargetLowering()
199 setOperationAction(ISD::SETCC, MVT::v2i1, Expand); in SITargetLowering()
200 setOperationAction(ISD::SETCC, MVT::v4i1, Expand); in SITargetLowering()
201 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); in SITargetLowering()
812 setTargetDAGCombine(ISD::SETCC); in SITargetLowering()
1603 if (VT == MVT::i1 && Op == ISD::SETCC) in isTypeDesirableForOp()
4704 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, DL, CCVT, LHS, RHS, in lowerICMPIntrinsic()
4734 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0, in lowerFCMPIntrinsic()
4747 if (Src.getOpcode() == ISD::SETCC) { in lowerBALLOTIntrinsic()
4749 return DAG.getNode(AMDGPUISD::SETCC, SL, VT, Src.getOperand(0), in lowerBALLOTIntrinsic()
[all …]
H A DAMDGPUInstrInfo.td199 def AMDGPUsetcc : SDNode<"AMDGPUISD::SETCC", AMDGPUSetCCOp>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp105 setTargetDAGCombine(ISD::SETCC); in MipsSETargetLowering()
128 setOperationAction(ISD::SETCC, MVT::f16, Promote); in MipsSETargetLowering()
247 setOperationAction(ISD::SETCC, MVT::i32, Legal); in MipsSETargetLowering()
251 setOperationAction(ISD::SETCC, MVT::f32, Legal); in MipsSETargetLowering()
256 setOperationAction(ISD::SETCC, MVT::f64, Legal); in MipsSETargetLowering()
294 setOperationAction(ISD::SETCC, MVT::i64, Legal); in MipsSETargetLowering()
362 setOperationAction(ISD::SETCC, Ty, Legal); in addMSAIntType()
399 setOperationAction(ISD::SETCC, Ty, Legal); in addMSAFloatType()
1051 case ISD::SETCC: in PerformDAGCombine()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp368 setOperationAction(ISD::SETCC, MVT::i32, Custom); in AArch64TargetLowering()
369 setOperationAction(ISD::SETCC, MVT::i64, Custom); in AArch64TargetLowering()
370 setOperationAction(ISD::SETCC, MVT::f16, Custom); in AArch64TargetLowering()
371 setOperationAction(ISD::SETCC, MVT::f32, Custom); in AArch64TargetLowering()
372 setOperationAction(ISD::SETCC, MVT::f64, Custom); in AArch64TargetLowering()
433 setOperationAction(ISD::SETCC, MVT::f128, Custom); in AArch64TargetLowering()
610 setOperationAction(ISD::SETCC, MVT::f16, Promote); in AArch64TargetLowering()
647 setOperationAction(ISD::SETCC, MVT::v4f16, Expand); in AArch64TargetLowering()
675 setOperationAction(ISD::SETCC, MVT::v8f16, Expand); in AArch64TargetLowering()
977 setOperationAction(ISD::SETCC, MVT::v1f64, Expand); in AArch64TargetLowering()
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