Searched refs:RootDef (Results 1 – 2 of 2) sorted by relevance
332 ComplexRendererFns tryFoldAddLowIntoImm(MachineInstr &RootDef, unsigned Size,5559 MachineInstr *RootDef = MRI.getVRegDef(Root.getReg()); in selectAddrModeUnscaled() local5560 if (!RootDef) in selectAddrModeUnscaled()5563 MachineOperand &OffImm = RootDef->getOperand(2); in selectAddrModeUnscaled()5579 MachineOperand &Base = RootDef->getOperand(1); in selectAddrModeUnscaled()5589 AArch64InstructionSelector::tryFoldAddLowIntoImm(MachineInstr &RootDef, in tryFoldAddLowIntoImm() argument5592 if (RootDef.getOpcode() != AArch64::G_ADD_LOW) in tryFoldAddLowIntoImm()5594 MachineInstr &Adrp = *MRI.getVRegDef(RootDef.getOperand(1).getReg()); in tryFoldAddLowIntoImm()5607 auto &MF = *RootDef.getParent()->getParent(); in tryFoldAddLowIntoImm()5612 MachineIRBuilder MIRBuilder(RootDef); in tryFoldAddLowIntoImm()[all …]
3740 if (const MachineInstr *RootDef = MRI->getVRegDef(Root.getReg())) { in selectMUBUFScratchOffen() local3755 } else if (RootDef->getOpcode() == AMDGPU::G_FRAME_INDEX) { in selectMUBUFScratchOffen()3756 FI = RootDef->getOperand(1).getIndex(); in selectMUBUFScratchOffen()3840 const MachineInstr *RootDef = MRI->getVRegDef(Root.getReg()); in selectDS1Addr1OffsetImpl() local3841 if (!RootDef) in selectDS1Addr1OffsetImpl()3856 } else if (RootDef->getOpcode() == AMDGPU::G_SUB) { in selectDS1Addr1OffsetImpl()3905 const MachineInstr *RootDef = MRI->getVRegDef(Root.getReg()); in selectDSReadWrite2Impl() local3906 if (!RootDef) in selectDSReadWrite2Impl()3923 } else if (RootDef->getOpcode() == AMDGPU::G_SUB) { in selectDSReadWrite2Impl()