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Searched refs:ResVT (Results 1 – 23 of 23) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2098 EVT ResVT = N->getValueType(0); in performVectorExtendCombine() local
2099 if (ResVT == MVT::v8i16) { in performVectorExtendCombine()
2103 } else if (ResVT == MVT::v4i32) { in performVectorExtendCombine()
2107 } else if (ResVT == MVT::v2i64) { in performVectorExtendCombine()
2123 return DAG.getNode(Op, SDLoc(N), ResVT, Source); in performVectorExtendCombine()
2131 EVT ResVT = N->getValueType(0); in performVectorConvertLowCombine() local
2132 if (ResVT != MVT::v2f64) in performVectorConvertLowCombine()
2158 return DAG.getNode(Op, SDLoc(N), ResVT, Source); in performVectorConvertLowCombine()
2184 return DAG.getNode(Op, SDLoc(N), ResVT, Source); in performVectorConvertLowCombine()
2202 EVT ResVT = N->getValueType(0); in performVectorTruncSatLowCombine() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp252 EVT ResVT = N->getValueType(0); in ScalarizeVecRes_OverflowOp() local
256 if (getTypeAction(ResVT) == TargetLowering::TypeScalarizeVector) { in ScalarizeVecRes_OverflowOp()
268 ResVT.getVectorElementType(), OvVT.getVectorElementType()); in ScalarizeVecRes_OverflowOp()
1524 EVT ResVT = N->getValueType(0); in SplitVecRes_OverflowOp() local
1527 std::tie(LoResVT, HiResVT) = DAG.GetSplitDestVTs(ResVT); in SplitVecRes_OverflowOp()
1531 if (getTypeAction(ResVT) == TargetLowering::TypeSplitVector) { in SplitVecRes_OverflowOp()
2289 EVT ResVT = N->getValueType(0); in SplitVecOp_VECREDUCE() local
2304 return DAG.getNode(N->getOpcode(), dl, ResVT, Partial, N->getFlags()); in SplitVecOp_VECREDUCE()
2308 EVT ResVT = N->getValueType(0); in SplitVecOp_VECREDUCE_SEQ() local
2323 SDValue Partial = DAG.getNode(N->getOpcode(), dl, ResVT, AccOp, Lo, Flags); in SplitVecOp_VECREDUCE_SEQ()
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H A DLegalizeIntegerTypes.cpp261 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); in PromoteIntRes_Atomic0() local
263 N->getMemoryVT(), ResVT, in PromoteIntRes_Atomic0()
4919 EVT ResVT = N->getValueType(0); in PromoteIntOp_CONCAT_VECTORS() local
4922 if (ResVT.isScalableVector()) { in PromoteIntOp_CONCAT_VECTORS()
4923 SDValue ResVec = DAG.getUNDEF(ResVT); in PromoteIntOp_CONCAT_VECTORS()
4928 ResVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ResVec, Op, in PromoteIntOp_CONCAT_VECTORS()
H A DSelectionDAG.cpp1751 SDValue SelectionDAG::getStepVector(const SDLoc &DL, EVT ResVT, SDValue Step) { in getStepVector() argument
1752 if (ResVT.isScalableVector()) in getStepVector()
1753 return getNode(ISD::STEP_VECTOR, DL, ResVT, Step); in getStepVector()
1758 for (uint64_t i = 0; i < ResVT.getVectorNumElements(); i++) in getStepVector()
1760 return getBuildVector(ResVT, DL, OpsStepConstants); in getStepVector()
9994 EVT ResVT = N->getValueType(0); in UnrollVectorOverflowOp() local
9996 EVT ResEltVT = ResVT.getVectorElementType(); in UnrollVectorOverflowOp()
10001 unsigned NE = ResVT.getVectorNumElements(); in UnrollVectorOverflowOp()
10020 getBoolConstant(true, dl, OvEltVT, ResVT), in UnrollVectorOverflowOp()
H A DDAGCombiner.cpp6670 EVT ResVT = ExtractFrom.getValueType(); in extractShiftForRotate() local
6672 return DAG.getNode(Opcode, DL, ResVT, OppShiftLHS, NewShiftNode); in extractShiftForRotate()
16034 EVT ResVT = Use->getValueType(0); in canMergeExpensiveCrossRegisterBankCopy() local
16036 TLI.getRegClassFor(ResVT.getSimpleVT(), Use->isDivergent()); in canMergeExpensiveCrossRegisterBankCopy()
16040 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT)) in canMergeExpensiveCrossRegisterBankCopy()
16054 ResVT.getTypeForEVT(*DAG->getContext())); in canMergeExpensiveCrossRegisterBankCopy()
16060 if (!TLI.isOperationLegal(ISD::LOAD, ResVT)) in canMergeExpensiveCrossRegisterBankCopy()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp4754 EVT ResVT = N->getValueType(0); in ReplaceLoadVector() local
4757 assert(ResVT.isVector() && "Vector load must have vector type"); in ReplaceLoadVector()
4762 assert(ResVT.isSimple() && "Can only handle simple types"); in ReplaceLoadVector()
4763 switch (ResVT.getSimpleVT().SimpleTy) { in ReplaceLoadVector()
4787 Align PrefAlign = TD.getPrefTypeAlign(ResVT.getTypeForEVT(*DAG.getContext())); in ReplaceLoadVector()
4797 EVT EltVT = ResVT.getVectorElementType(); in ReplaceLoadVector()
4798 unsigned NumElts = ResVT.getVectorNumElements(); in ReplaceLoadVector()
4868 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res); in ReplaceLoadVector()
4875 SDValue BuildVec = DAG.getBuildVector(ResVT, DL, ScalarRes); in ReplaceLoadVector()
4898 EVT ResVT = N->getValueType(0); in ReplaceINTRINSIC_W_CHAIN() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1619 EVT ResVT = TLI->getValueType(DL, ResTy); in getExtendedAddReductionCost() local
1620 if (ST->hasMVEIntegerOps() && ValVT.isSimple() && ResVT.isSimple()) { in getExtendedAddReductionCost()
1623 if ((LT.second == MVT::v16i8 && ResVT.getSizeInBits() <= 32) || in getExtendedAddReductionCost()
1625 ResVT.getSizeInBits() <= (IsMLA ? 64 : 32)) || in getExtendedAddReductionCost()
1626 (LT.second == MVT::v4i32 && ResVT.getSizeInBits() <= 64)) in getExtendedAddReductionCost()
H A DARMISelLowering.cpp15564 EVT ResVT = N->getValueType(0); in PerformVECREDUCE_ADDCombine() local
15592 if (ResVT != RetTy || N0->getOpcode() != ExtendCode) in PerformVECREDUCE_ADDCombine()
15601 if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT || in PerformVECREDUCE_ADDCombine()
15623 if (ResVT != RetTy) in PerformVECREDUCE_ADDCombine()
15628 ResVT.getScalarSizeInBits()) in PerformVECREDUCE_ADDCombine()
15655 if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT || in PerformVECREDUCE_ADDCombine()
15662 ResVT.getScalarSizeInBits()) in PerformVECREDUCE_ADDCombine()
15688 return DAG.getNode(ARMISD::VADDVs, dl, ResVT, A); in PerformVECREDUCE_ADDCombine()
15690 return DAG.getNode(ARMISD::VADDVu, dl, ResVT, A); in PerformVECREDUCE_ADDCombine()
15698 return DAG.getNode(ISD::TRUNCATE, dl, ResVT, in PerformVECREDUCE_ADDCombine()
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H A DARMISelLowering.h603 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp11865 bool AArch64TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
11867 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
11870 return (Index == 0 || Index == ResVT.getVectorNumElements()); in isExtractSubvectorCheap()
14576 EVT ResVT = N->getValueType(0); in performUzpCombine() local
14582 return DAG.getNode(AArch64ISD::UZP1, DL, ResVT, X, Op1); in performUzpCombine()
14590 return DAG.getNode(AArch64ISD::UZP1, DL, ResVT, Op0, Z); in performUzpCombine()
14622 EVT ResVT = N->getValueType(0); in performGLD1Combine() local
14646 return DAG.getNode(NewOpc, DL, {ResVT, MVT::Other}, in performGLD1Combine()
15432 EVT ResVT = N->getValueType(0); in performVSelectCombine() local
15436 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits()) in performVSelectCombine()
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H A DAArch64ISelLowering.h642 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
H A DAArch64InstrInfo.td5322 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
5325 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
5329 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
5342 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
5344 def : Pat<(ResVT (AArch64dup (i32 (trunc (extractelt (v2i64 V128:$Rn),
5348 def : Pat<(ResVT (AArch64dup (i32 (trunc (extractelt (v1i64 V64:$Rn),
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp3327 EVT ResVT = Op.getValueType(); in lowerBITCAST() local
3334 SDValue NewLoad = DAG.getLoad(ResVT, DL, LoadN->getChain(), in lowerBITCAST()
3341 if (InVT == MVT::i32 && ResVT == MVT::f32) { in lowerBITCAST()
3357 if (InVT == MVT::f32 && ResVT == MVT::i32) { in lowerBITCAST()
5723 SDValue SystemZTargetLowering::combineExtract(const SDLoc &DL, EVT ResVT, in combineExtract() argument
5751 return DAG.getUNDEF(ResVT); in combineExtract()
5781 EVT VT = MVT::getIntegerVT(ResVT.getSizeInBits()); in combineExtract()
5783 if (VT != ResVT) { in combineExtract()
5785 Op = DAG.getNode(ISD::BITCAST, DL, ResVT, Op); in combineExtract()
5821 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Op, in combineExtract()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86FastISel.cpp3564 EVT ResVT = VA.getValVT(); in fastLowerCall() local
3565 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; in fastLowerCall()
3566 unsigned MemSize = ResVT.getSizeInBits()/8; in fastLowerCall()
3571 Opc = ResVT == MVT::f32 ? X86::MOVSSrm_alt : X86::MOVSDrm_alt; in fastLowerCall()
H A DX86ISelLowering.h1302 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
H A DX86ISelLowering.cpp5329 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
5331 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
5336 if (ResVT.getVectorElementType() == MVT::i1) in isExtractSubvectorCheap()
5337 return Index == 0 || ((ResVT.getSizeInBits() == SrcVT.getSizeInBits()*2) && in isExtractSubvectorCheap()
5338 (Index == ResVT.getVectorNumElements())); in isExtractSubvectorCheap()
5340 return (Index % ResVT.getVectorNumElements()) == 0; in isExtractSubvectorCheap()
10697 MVT ResVT = Op.getSimpleValueType(); in LowerAVXCONCAT_VECTORS() local
10699 assert((ResVT.is256BitVector() || in LowerAVXCONCAT_VECTORS()
10700 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide"); in LowerAVXCONCAT_VECTORS()
10721 MVT HalfVT = ResVT.getHalfNumVectorElementsVT(); in LowerAVXCONCAT_VECTORS()
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H A DX86ISelDAGToDAG.cpp4457 MVT ResVT = Setcc.getSimpleValueType(); in tryVPTESTM() local
4458 MVT MaskVT = ResVT; in tryVPTESTM()
4513 unsigned RegClass = TLI->getRegClassFor(ResVT)->getID(); in tryVPTESTM()
4516 dl, ResVT, SDValue(CNode, 0), RC); in tryVPTESTM()
H A DX86InstrSSE.td6972 ValueType ResVT, ValueType OpVT, SchedWrite Sched> :
6975 [(set RC:$dst, (ResVT (X86VBroadcast (OpVT VR128:$src))))]>,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp7790 EVT ResVT = Op.getValueType(); in LowerSELECT_CC() local
7849 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
7852 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
7862 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
7871 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
7885 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
7888 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
7895 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
7901 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
7907 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
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H A DPPCISelDAGToDAG.cpp4401 EVT ResVT = VecVT.changeVectorElementTypeToInteger(); in trySETCC() local
4403 SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, ResVT, LHS, RHS), 0); in trySETCC()
4405 ResVT, VCmp, VCmp); in trySETCC()
4409 CurDAG->SelectNodeTo(N, VCmpInst, ResVT, LHS, RHS); in trySETCC()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h838 SDValue getStepVector(const SDLoc &DL, EVT ResVT, SDValue Step);
H A DTargetLowering.h2749 virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonPatterns.td322 class OpR_R_pat<InstHexagon MI, PatFrag Op, ValueType ResVT, PatFrag RegPred>
323 : Pat<(ResVT (Op RegPred:$Rs)), (MI RegPred:$Rs)>;