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Searched refs:Regs (Results 1 – 25 of 143) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64LowerHomogeneousPrologEpilog.cpp129 static std::string getFrameHelperName(SmallVectorImpl<unsigned> &Regs, in getFrameHelperName() argument
147 for (auto Reg : Regs) in getFrameHelperName()
272 SmallVectorImpl<unsigned> &Regs, in getOrCreateFrameHelper() argument
275 assert(Regs.size() >= 2); in getOrCreateFrameHelper()
276 auto Name = getFrameHelperName(Regs, Type, FpOffset); in getOrCreateFrameHelper()
286 int Size = (int)Regs.size(); in getOrCreateFrameHelper()
292 Regs.begin(), std::find(Regs.begin(), Regs.end(), AArch64::LR)); in getOrCreateFrameHelper()
297 assert(Regs[Size - 2] != AArch64::LR); in getOrCreateFrameHelper()
298 emitStore(MF, MBB, MBB.end(), TII, Regs[Size - 2], Regs[Size - 1], in getOrCreateFrameHelper()
305 if (Regs[I - 1] == AArch64::LR) in getOrCreateFrameHelper()
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H A DAArch64ISelDAGToDAG.cpp1190 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { in createDTuple() argument
1196 return createTuple(Regs, RegClassIDs, SubRegs); in createDTuple()
1199 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple() argument
1205 return createTuple(Regs, RegClassIDs, SubRegs); in createQTuple()
1208 SDValue AArch64DAGToDAGISel::createZTuple(ArrayRef<SDValue> Regs) { in createZTuple() argument
1215 return createTuple(Regs, RegClassIDs, SubRegs); in createZTuple()
1218 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, in createTuple() argument
1223 if (Regs.size() == 1) in createTuple()
1224 return Regs[0]; in createTuple()
1226 assert(Regs.size() >= 2 && Regs.size() <= 4); in createTuple()
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h336 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated() argument
337 for (unsigned i = 0; i < Regs.size(); ++i) in getFirstUnallocated()
338 if (!isAllocated(Regs[i])) in getFirstUnallocated()
340 return Regs.size(); in getFirstUnallocated()
370 MCPhysReg AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg() argument
371 unsigned FirstUnalloc = getFirstUnallocated(Regs); in AllocateReg()
372 if (FirstUnalloc == Regs.size()) in AllocateReg()
376 MCPhysReg Reg = Regs[FirstUnalloc]; in AllocateReg()
384 MCPhysReg AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock() argument
385 if (RegsRequired > Regs.size()) in AllocateRegBlock()
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H A DRegisterPressure.h275 RegSet Regs; variable
297 RegSet::const_iterator I = Regs.find(SparseIndex); in contains()
298 if (I == Regs.end()) in contains()
307 auto InsertRes = Regs.insert(IndexMaskPair(SparseIndex, Pair.LaneMask)); in insert()
320 RegSet::iterator I = Regs.find(SparseIndex); in erase()
321 if (I == Regs.end()) in erase()
329 return Regs.size(); in size()
334 for (const IndexMaskPair &P : Regs) { in appendTo()
411 void addLiveRegs(ArrayRef<RegisterMaskPair> Regs);
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp83 const unsigned *Regs, unsigned Size) { in decodeRegisterClass() argument
85 RegNo = Regs[RegNo]; in decodeRegisterClass()
292 const unsigned *Regs) { in decodeBDAddr12Operand() argument
296 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
302 const unsigned *Regs) { in decodeBDAddr20Operand() argument
306 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
312 const unsigned *Regs) { in decodeBDXAddr12Operand() argument
317 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
319 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index])); in decodeBDXAddr12Operand()
324 const unsigned *Regs) { in decodeBDXAddr20Operand() argument
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp217 SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx), in splitToValueTypes()
224 assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch"); in splitToValueTypes()
230 SplitArgs.emplace_back(OrigArg.Regs[i], SplitTy, OrigArg.Flags[0], in splitToValueTypes()
314 ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT, in buildCopyFromRegs() argument
321 assert(OrigRegs[0] == Regs[0]); in buildCopyFromRegs()
326 Regs.size() == 1) { in buildCopyFromRegs()
327 B.buildBitcast(OrigRegs[0], Regs[0]); in buildCopyFromRegs()
337 OrigRegs.size() == 1 && Regs.size() == 1) { in buildCopyFromRegs()
338 Register SrcReg = Regs[0]; in buildCopyFromRegs()
358 unsigned SrcSize = PartLLT.getSizeInBits() * Regs.size(); in buildCopyFromRegs()
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H A DInlineAsmLowering.cpp40 SmallVector<Register, 1> Regs; member in __anond54b29330111::GISelAsmOperandInfo
137 OpInfo.Regs.push_back(R); in getRegistersForValue()
399 if (OpInfo.Regs.empty()) { in lowerInlineAsm()
410 OpInfo.Regs.size()); in lowerInlineAsm()
411 if (OpInfo.Regs.front().isVirtual()) { in lowerInlineAsm()
416 const TargetRegisterClass *RC = MRI->getRegClass(OpInfo.Regs.front()); in lowerInlineAsm()
422 for (Register Reg : OpInfo.Regs) { in lowerInlineAsm()
545 if (OpInfo.Regs.empty()) { in lowerInlineAsm()
552 unsigned NumRegs = OpInfo.Regs.size(); in lowerInlineAsm()
565 if (OpInfo.Regs.front().isVirtual()) { in lowerInlineAsm()
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/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp86 void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs,
89 const std::deque<CodeGenRegister> &Regs,
218 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure() local
220 if (Regs.empty() || RC.Artificial) in EmitRegUnitPressure()
383 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables() argument
389 for (auto &RE : Regs) { in EmitRegMappingTables()
405 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); in EmitRegMappingTables()
450 for (auto &RE : Regs) { in EmitRegMappingTables()
510 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping() argument
514 for (auto &RE : Regs) { in EmitRegMapping()
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H A DCodeGenRegisters.cpp209 RegUnitIterator(const CodeGenRegister::Vec &Regs): in RegUnitIterator() argument
210 RegI(Regs.begin()), RegE(Regs.end()) { in RegUnitIterator()
1121 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); in CodeGenRegBank() local
1122 llvm::sort(Regs, LessRecordRegister()); in CodeGenRegBank()
1124 for (unsigned i = 0, e = Regs.size(); i != e; ++i) in CodeGenRegBank()
1125 getReg(Regs[i]); in CodeGenRegBank()
1580 CodeGenRegister::Vec Regs; member
1609 const CodeGenRegister::Vec &Regs = RegClass.getMembers(); in computeUberSets() local
1610 if (Regs.empty()) in computeUberSets()
1613 unsigned USetID = UberSetIDs.findLeader((*Regs.begin())->EnumValue); in computeUberSets()
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
H A DCallLowering.h62 SmallVector<Register, 4> Regs; member
74 ArgInfo(ArrayRef<Register> Regs, Type *Ty,
77 : BaseArgInfo(Ty, Flags, IsFixed), Regs(Regs.begin(), Regs.end()), in BaseArgInfo()
79 if (!Regs.empty() && Flags.empty()) in BaseArgInfo()
83 (Regs.empty() || Regs[0] == 0)) && in BaseArgInfo()
87 ArgInfo(ArrayRef<Register> Regs, const Value &OrigValue,
90 : ArgInfo(Regs, OrigValue.getType(), Flags, IsFixed, &OrigValue) {}
271 assignValueToAddress(Arg.Regs[ValRegIndex], Addr, Size, MPO, VA); in assignValueToAddress()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMUnwindOpAsm.cpp107 for (uint32_t Regs : {VFPRegSave & 0xffff0000u, VFPRegSave & 0x0000ffffu}) { in EmitVFPRegSave()
108 while (Regs) { in EmitVFPRegSave()
110 auto RangeMSB = 32 - countLeadingZeros(Regs); in EmitVFPRegSave()
111 auto RangeLen = countLeadingOnes(Regs << (32 - RangeMSB)); in EmitVFPRegSave()
121 Regs &= ~(-1u << RangeLSB); in EmitVFPRegSave()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MCA/
H A DHWEventListener.h74 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, in HWInstructionDispatchedEvent() argument
77 UsedPhysRegs(Regs), MicroOpcodes(UOps) {} in HWInstructionDispatchedEvent()
95 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent() argument
97 FreedPhysRegs(Regs) {} in HWInstructionRetiredEvent()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp865 const unsigned *Regs; in parseRegister() local
867 case GR32Reg: Regs = SystemZMC::GR32Regs; break; in parseRegister()
868 case GRH32Reg: Regs = SystemZMC::GRH32Regs; break; in parseRegister()
869 case GR64Reg: Regs = SystemZMC::GR64Regs; break; in parseRegister()
870 case GR128Reg: Regs = SystemZMC::GR128Regs; break; in parseRegister()
871 case FP32Reg: Regs = SystemZMC::FP32Regs; break; in parseRegister()
872 case FP64Reg: Regs = SystemZMC::FP64Regs; break; in parseRegister()
873 case FP128Reg: Regs = SystemZMC::FP128Regs; break; in parseRegister()
874 case VR32Reg: Regs = SystemZMC::VR32Regs; break; in parseRegister()
875 case VR64Reg: Regs = SystemZMC::VR64Regs; break; in parseRegister()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp240 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getCalleeSavedRegs() local
242 return Regs->getCalleeSavedRegs(MF); in getCalleeSavedRegs()
250 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getCallPreservedMask() local
251 return Regs->getCallPreservedMask(MF, CC); in getCallPreservedMask()
259 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getReservedRegs() local
262 for (MCRegAliasIterator AI(Regs->getFramePointerRegister(), this, true); in getReservedRegs()
267 for (MCRegAliasIterator AI(Regs->getStackPointerRegister(), this, true); in getReservedRegs()
451 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters(); in getFrameRegister() local
453 return TFI->hasFP(MF) ? Regs->getFramePointerRegister() in getFrameRegister()
454 : Regs->getStackPointerRegister(); in getFrameRegister()
/netbsd-src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Checkers/
H A DTaint.cpp136 TaintedSubRegions Regs = SavedRegs ? *SavedRegs : F.getEmptyMap(); in addPartialTaint() local
138 Regs = F.add(Regs, SubRegion, Kind); in addPartialTaint()
139 ProgramStateRef NewState = State->set<DerivedSymTaint>(ParentSym, Regs); in addPartialTaint()
202 if (const TaintedSubRegions *Regs = in isTainted() local
205 for (auto I : *Regs) { in isTainted()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp67 static SDValue createTupleImpl(SelectionDAG &CurDAG, ArrayRef<SDValue> Regs, in createTupleImpl() argument
69 assert(Regs.size() >= 2 && Regs.size() <= 8); in createTupleImpl()
71 SDLoc DL(Regs[0]); in createTupleImpl()
76 for (unsigned I = 0; I < Regs.size(); ++I) { in createTupleImpl()
77 Ops.push_back(Regs[I]); in createTupleImpl()
85 static SDValue createM1Tuple(SelectionDAG &CurDAG, ArrayRef<SDValue> Regs, in createM1Tuple() argument
92 return createTupleImpl(CurDAG, Regs, RegClassIDs[NF - 2], RISCV::sub_vrm1_0); in createM1Tuple()
95 static SDValue createM2Tuple(SelectionDAG &CurDAG, ArrayRef<SDValue> Regs, in createM2Tuple() argument
101 return createTupleImpl(CurDAG, Regs, RegClassIDs[NF - 2], RISCV::sub_vrm2_0); in createM2Tuple()
104 static SDValue createM4Tuple(SelectionDAG &CurDAG, ArrayRef<SDValue> Regs, in createM4Tuple() argument
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUPALMetadata.cpp162 auto Regs = getRegisters(); in getRegister() local
163 auto It = Regs.find(MsgPackDoc.getNode(Reg)); in getRegister()
164 if (It == Regs.end()) in getRegister()
648 auto Regs = getRegisters(); in toString() local
649 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) { in toString()
650 if (I != Regs.begin()) in toString()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.cpp80 std::vector<unsigned> &Regs, in GetGroupRegs() argument
85 Regs.push_back(Reg); in GetGroupRegs()
554 std::vector<unsigned> Regs; in FindSuitableFreeRegisters() local
555 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs); in FindSuitableFreeRegisters()
556 assert(!Regs.empty() && "Empty register group!"); in FindSuitableFreeRegisters()
557 if (Regs.empty()) in FindSuitableFreeRegisters()
567 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in FindSuitableFreeRegisters()
568 unsigned Reg = Regs[i]; in FindSuitableFreeRegisters()
590 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in FindSuitableFreeRegisters()
591 unsigned Reg = Regs[i]; in FindSuitableFreeRegisters()
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H A DExecutionDomainFix.cpp329 SmallVector<int, 4> Regs; in visitSoftInstr() local
341 auto I = partition_point(Regs, [&](int I) { in visitSoftInstr()
344 Regs.insert(I, rx); in visitSoftInstr()
350 while (!Regs.empty()) { in visitSoftInstr()
352 dv = LiveRegs[Regs.pop_back_val()]; in visitSoftInstr()
359 DomainValue *Latest = LiveRegs[Regs.pop_back_val()]; in visitSoftInstr()
H A DRDFRegisters.cpp102 AliasInfos[U].Regs = AS; in PhysicalRegisterInfo()
333 BitVector Regs = PRI.getUnitAliases(U); in makeRegRef() local
339 Regs &= PRI.getUnitAliases(U); in makeRegRef()
347 int F = Regs.find_first(); in makeRegRef()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMFrameLowering.cpp1084 SmallVector<RegAndKill, 4> Regs; in emitPushInst() local
1111 Regs.push_back(std::make_pair(Reg, /*isKill=*/!isLiveIn)); in emitPushInst()
1114 if (Regs.empty()) in emitPushInst()
1117 llvm::sort(Regs, [&](const RegAndKill &LHS, const RegAndKill &RHS) { in emitPushInst()
1121 if (Regs.size() > 1 || StrOpc== 0) { in emitPushInst()
1126 for (unsigned i = 0, e = Regs.size(); i < e; ++i) in emitPushInst()
1127 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); in emitPushInst()
1128 } else if (Regs.size() == 1) { in emitPushInst()
1130 .addReg(Regs[0].first, getKillRegState(Regs[0].second)) in emitPushInst()
1136 Regs.clear(); in emitPushInst()
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H A DARMLoadStoreOptimizer.cpp178 ArrayRef<std::pair<unsigned, bool>> Regs,
184 ArrayRef<std::pair<unsigned, bool>> Regs,
614 static bool ContainsReg(const ArrayRef<std::pair<unsigned, bool>> &Regs, in ContainsReg() argument
616 for (const std::pair<unsigned, bool> &R : Regs) in ContainsReg()
629 ArrayRef<std::pair<unsigned, bool>> Regs, in CreateLoadStoreMulti() argument
631 unsigned NumRegs = Regs.size(); in CreateLoadStoreMulti()
645 if (isThumb1 && ContainsReg(Regs, Base)) { in CreateLoadStoreMulti()
685 NewBase = Regs[NumRegs-1].first; in CreateLoadStoreMulti()
693 for (const std::pair<unsigned, bool> &R : Regs) in CreateLoadStoreMulti()
727 (!isi32Store(Opcode) || !ContainsReg(Regs, Base)); in CreateLoadStoreMulti()
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/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
H A DRegisterAliasing.cpp82 std::string debugString(const MCRegisterInfo &RegInfo, const BitVector &Regs) { in debugString() argument
84 for (const unsigned Reg : Regs.set_bits()) { in debugString()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonGenInsert.cpp999 RegisterSet Regs[2]; in findRemovableRegisters() local
1002 Regs[S].insert(VR); in findRemovableRegisters()
1004 while (!Regs[S].empty()) { in findRemovableRegisters()
1007 Regs[OtherS].clear(); in findRemovableRegisters()
1008 for (unsigned R = Regs[S].find_first(); R; R = Regs[S].find_next(R)) { in findRemovableRegisters()
1009 Regs[S].remove(R); in findRemovableRegisters()
1032 getInstrUses(DefI, Regs[OtherS]); in findRemovableRegisters()
1477 SmallVector<unsigned,2> Regs; in removeDeadCode() local
1486 Regs.push_back(R); in removeDeadCode()
1492 for (unsigned I = 0, N = Regs.size(); I != N; ++I) in removeDeadCode()
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/netbsd-src/external/gpl3/binutils.old/dist/gas/doc/
H A Dc-metag.texi60 * Meta-Regs:: Register Names
79 @node Meta-Regs

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