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Searched refs:RegisterFile (Results 1 – 17 of 17) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp62 RegisterFile::RegisterFile(const MCSchedModel &SM, const MCRegisterInfo &mri, in RegisterFile() function in llvm::mca::RegisterFile
70 void RegisterFile::initialize(const MCSchedModel &SM, unsigned NumRegs) { in initialize()
98 void RegisterFile::cycleStart() { in cycleStart()
103 void RegisterFile::onInstructionExecuted(Instruction *IS) { in onInstructionExecuted()
140 void RegisterFile::addRegisterFile(const MCRegisterFileDesc &RF, in addRegisterFile()
191 void RegisterFile::allocatePhysRegs(const RegisterRenamingInfo &Entry, in allocatePhysRegs()
206 void RegisterFile::freePhysRegs(const RegisterRenamingInfo &Entry, in freePhysRegs()
221 void RegisterFile::addRegisterWrite(WriteRef Write, in addRegisterWrite()
308 void RegisterFile::removeRegisterWrite( in removeRegisterWrite()
356 bool RegisterFile::canEliminateMove(const WriteState &WS, const ReadState &RS, in canEliminateMove()
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MCA/Stages/
H A DInOrderIssueStage.h28 class RegisterFile; variable
34 RegisterFile &PRF;
82 InOrderIssueStage(RegisterFile &PRF, const MCSchedModel &SM, in InOrderIssueStage()
H A DRetireStage.h31 RegisterFile &PRF;
38 RetireStage(RetireControlUnit &R, RegisterFile &F, LSUnitBase &LS) in RetireStage()
H A DDispatchStage.h56 RegisterFile &PRF;
70 RegisterFile &F);
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/
H A DContext.cpp40 auto PRF = std::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize); in createDefaultPipeline()
74 auto PRF = std::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize); in createInOrderPipeline()
H A DCMakeLists.txt7 HardwareUnits/RegisterFile.cpp
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MCA/HardwareUnits/
H A DRegisterFile.h83 class RegisterFile : public HardwareUnit {
232 RegisterFile(const MCSchedModel &SM, const MCRegisterInfo &mri,
/netbsd-src/external/apache2/llvm/dist/llvm/utils/gn/secondary/llvm/lib/MCA/
H A DBUILD.gn15 "HardwareUnits/RegisterFile.cpp",
/netbsd-src/external/apache2/llvm/lib/libLLVMMCA/
H A DMakefile22 RegisterFile.cpp \
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/Stages/
H A DInOrderIssueStage.cpp92 static unsigned checkRegisterHazard(const RegisterFile &PRF, in checkRegisterHazard()
176 static void addRegisterReadWrite(RegisterFile &PRF, Instruction &IS, in addRegisterReadWrite()
H A DDispatchStage.cpp31 RegisterFile &F) in DispatchStage()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ScheduleBtVer2.td50 def JIntegerPRF : RegisterFile<64, [GR64, CCR], [1, 1], [1, 0],
63 def JFpuPRF: RegisterFile<72, [VR64, VR128, VR256], [1, 1, 2], [1, 1, 0],
H A DX86ScheduleBdVer2.td98 def PdIntegerPRF : RegisterFile<96, [GR64, CCR]>;
115 def PdFpuPRF : RegisterFile<160, [VR64, VR128, VR256], [1, 1, 2]>;
H A DX86ScheduleZnver2.td103 def Zn2IntegerPRF : RegisterFile<168, [GR64, CCR]>;
113 def Zn2FpuPRF: RegisterFile<160, [VR64, VR128, VR256], [1, 1, 2]>;
H A DX86ScheduleZnver1.td102 def ZnIntegerPRF : RegisterFile<168, [GR64, CCR]>;
112 def ZnFpuPRF: RegisterFile<160, [VR64, VR128, VR256], [1, 1, 2]>;
H A DX86ScheduleZnver3.td160 def Zn3IntegerPRF : RegisterFile<192, [GR64, CCR], [1, 1], [1, 0],
338 def Zn3FpPRF : RegisterFile<160, [VR64, VR128, VR256], [1, 1, 1], [0, 1, 1],
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/
H A DTargetSchedule.td538 class RegisterFile<int numPhysRegs, list<RegisterClass> Classes = [],