| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | RegisterBank.cpp | 22 const unsigned RegisterBank::InvalidID = UINT_MAX; 24 RegisterBank::RegisterBank( in RegisterBank() function in RegisterBank 32 bool RegisterBank::verify(const TargetRegisterInfo &TRI) const { in verify() 61 bool RegisterBank::covers(const TargetRegisterClass &RC) const { in covers() 66 bool RegisterBank::isValid() const { in isValid() 72 bool RegisterBank::operator==(const RegisterBank &OtherRB) const { in operator ==() 82 LLVM_DUMP_METHOD void RegisterBank::dump(const TargetRegisterInfo *TRI) const { in dump() 87 void RegisterBank::print(raw_ostream &OS, bool IsForDebug, in print()
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| H A D | RegisterBankInfo.cpp | 58 RegisterBankInfo::RegisterBankInfo(RegisterBank **RegBanks, in RegisterBankInfo() 72 const RegisterBank &RegBank = getRegBank(Idx); in verify() 82 const RegisterBank * 93 if (auto *RB = RegClassOrBank.dyn_cast<const RegisterBank *>()) in getRegBank() 112 const RegisterBank *RegisterBankInfo::getRegBankFromConstraints( in getRegBankFromConstraints() 125 const RegisterBank &RegBank = getRegBankFromRegClass(*RC, MRI.getType(Reg)); in getRegBankFromConstraints() 140 const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>(); in constrainGenericRegister() 196 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI); in getInstrMappingImpl() 200 const RegisterBank *CurRegBank = IsCopyLike ? AltRegBank : nullptr; in getInstrMappingImpl() 241 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI); in getInstrMappingImpl() [all …]
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| H A D | RegBankSelect.cpp | 121 const RegisterBank *CurRegBank = RBI->getRegBank(Reg, *MRI, *TRI); in assignmentMatch() 122 const RegisterBank *DesiredRegBank = ValMapping.BreakDown[0].RegBank; in assignmentMatch() 244 const RegisterBank *CurRegBank = RBI->getRegBank(MO.getReg(), *MRI, *TRI); in getRepairCost() 263 const RegisterBank *DesiredRegBank = ValMapping.BreakDown[0].RegBank; in getRepairCost() 633 const RegisterBank *RB = MRI->getRegBankOrNull(MI.getOperand(1).getReg()); in assignInstr()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | RegisterBankInfo.h | 33 class RegisterBank; variable 60 const RegisterBank *RegBank; 66 const RegisterBank &RegBank) in PartialMapping() 388 RegisterBank **RegBanks; 419 RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks); 432 RegisterBank &getRegBank(unsigned ID) { in getRegBank() 464 const RegisterBank &RegBank) const; 472 const RegisterBank &RegBank) const; 545 const RegisterBank * 576 const RegisterBank &getRegBank(unsigned ID) const { in getRegBank() [all …]
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| H A D | RegisterBank.h | 28 class RegisterBank { 43 RegisterBank(unsigned ID, const char *Name, unsigned Size, 74 bool operator==(const RegisterBank &OtherRB) const; 75 bool operator!=(const RegisterBank &OtherRB) const { 92 inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) {
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| H A D | CSEInfo.h | 164 class RegisterBank; variable 181 const GISelInstProfileBuilder &addNodeIDRegType(const RegisterBank *RB) const;
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| /netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | RegisterBankEmitter.cpp | 29 class RegisterBank { class 44 RegisterBank(const Record &TheDef) in RegisterBank() function in __anon2e4a08010111::RegisterBank 109 const std::vector<RegisterBank> &Banks); 111 const std::vector<RegisterBank> &Banks); 113 std::vector<RegisterBank> &Banks); 127 const std::vector<RegisterBank> &Banks) { in emitHeader() 146 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition() 214 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation() 283 std::vector<RegisterBank> Banks; in run() 286 RegisterBank Bank(*V); in run()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBanks.td | 9 def SGPRRegBank : RegisterBank<"SGPR", 13 def VGPRRegBank : RegisterBank<"VGPR", 18 def VCCRegBank : RegisterBank <"VCC", [SReg_1]>; 20 def AGPRRegBank : RegisterBank <"AGPR",
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| H A D | AMDGPURegisterBankInfo.h | 167 unsigned copyCost(const RegisterBank &A, const RegisterBank &B, 171 const RegisterBank *CurBank = nullptr) const override; 173 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
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| H A D | AMDGPURegisterBankInfo.cpp | 101 const RegisterBank *NewBank; 106 MachineRegisterInfo &MRI_, const RegisterBank *RB) in ApplyRegBankMapping() 124 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, MRI, *RBI.TRI); in applyBank() 150 const RegisterBank *DstBank = RBI.getRegBank(DstReg, MRI, *RBI.TRI); in applyBank() 164 const RegisterBank *RB = NewBank; in applyBank() 214 static bool isVectorRegisterBank(const RegisterBank &Bank) { in isVectorRegisterBank() 219 unsigned AMDGPURegisterBankInfo::copyCost(const RegisterBank &Dst, in copyCost() 220 const RegisterBank &Src, in copyCost() 252 const RegisterBank *CurBank) const { in getBreakDownCost() 275 const RegisterBank & [all …]
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| H A D | AMDGPUInstructionSelector.cpp | 87 const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>(); in isVCC() 218 const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>(); in selectPHI() 283 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_AND_OR_XOR() 310 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_ADD_SUB() 482 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_EXTRACT() 514 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_MERGE_VALUES() 556 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_UNMERGE_VALUES() 599 const RegisterBank *DstBank = RBI.getRegBank(Dst, *MRI, TRI); in selectG_BUILD_VECTOR_TRUNC() 724 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_INSERT() 730 const RegisterBank *Src0Bank = RBI.getRegBank(Src0Reg, *MRI, TRI); in selectG_INSERT() [all …]
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| H A D | SIRegisterInfo.h | 25 class RegisterBank; variable 264 const RegisterBank &Bank, 269 const RegisterBank &Bank, in getRegClassForTypeOnBank()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.h | 65 unsigned ValLength, const RegisterBank &RB); 136 unsigned copyCost(const RegisterBank &A, const RegisterBank &B, 139 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
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| H A D | AArch64RegisterBankInfo.cpp | 53 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo() 58 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo() 63 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo() 213 unsigned AArch64RegisterBankInfo::copyCost(const RegisterBank &A, in copyCost() 214 const RegisterBank &B, in copyCost() 234 const RegisterBank & 622 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping() 623 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping() 647 const RegisterBank &DstRB = in getInstrMapping() 649 const RegisterBank &SrcRB = in getInstrMapping()
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| H A D | AArch64InstructionSelector.cpp | 151 const RegisterBank &RB, 263 const RegisterBank &DstRB, LLT ScalarTy, 483 getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB, in getRegClassForTypeOnBank() 516 getMinClassForRegBank(const RegisterBank &RB, unsigned SizeInBits, in getMinClassForRegBank() 580 static unsigned getMinSizeForRegBank(const RegisterBank &RB) { in getMinSizeForRegBank() 628 const RegisterBank *PrevOpBank = nullptr; in unsupportedBinOp() 645 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI); in unsupportedBinOp() 771 static bool isValidCopy(const MachineInstr &I, const RegisterBank &DstBank, in isValidCopy() 835 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in getRegClassesForCopy() 836 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in getRegClassesForCopy() [all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterBanks.td | 13 def GPRRegBank : RegisterBank<"GPR", [XSeqPairsClass]>; 16 def FPRRegBank : RegisterBank<"FPR", [QQQQ]>; 19 def CCRegBank : RegisterBank<"CC", [CCR]>;
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/MIRParser/ |
| H A D | MIParser.h | 27 class RegisterBank; variable 42 const RegisterBank *RegBank; 49 using Name2RegBankMap = StringMap<const RegisterBank *>; 147 const RegisterBank *getRegBank(StringRef Name);
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsRegisterBanks.td | 12 def GPRBRegBank : RegisterBank<"GPRB", [GPR32]>; 14 def FPRBRegBank : RegisterBank<"FPRB", [FGR64, AFGR64, MSA128D]>;
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/GlobalISel/ |
| H A D | RegisterBank.td | 1 //===- RegisterBank.td - Register bank definitions ---------*- tablegen -*-===// 12 class RegisterBank<string name, list<RegisterClass> classes> {
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterBanks.td | 12 def GPRRegBank : RegisterBank<"GPRB", [GPR, GPRwithAPSR]>; 13 def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;
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| H A D | ARMRegisterBankInfo.h | 35 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86RegisterBanks.td | 13 def GPRRegBank : RegisterBank<"GPR", [GR64]>; 16 def VECRRegBank : RegisterBank<"VECR", [VR512]>;
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| H A D | X86InstructionSelector.cpp | 74 unsigned getLoadStoreOp(const LLT &Ty, const RegisterBank &RB, unsigned Opc, 128 const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const; 170 X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const { in getRegClass() 200 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass() 236 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy() 240 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy() 396 const RegisterBank &RB, in getLoadStoreOp() 510 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in selectLoadStoreOp() 719 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectTruncOrPtrToInt() 720 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectTruncOrPtrToInt() [all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVRegisterBanks.td | 13 def GPRRegBank : RegisterBank<"GPRB", [GPR]>;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCRegisterBanks.td | 15 def GPRRegBank : RegisterBank<"GPR", [G8RC]>;
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