| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.td | 1075 class ZPRExtendAsmOperand<string ShiftExtend, int RegWidth, int Scale,
1077 let Name = "ZPRExtend" # ShiftExtend # RegWidth # Scale
1081 # RegWidth # ", AArch64::ZPRRegClassID, "
1086 let DiagnosticType = "InvalidZPR" # RegWidth # ShiftExtend # Scale;
1092 int RegWidth, int Scale, string Suffix = "">
1095 !cast<AsmOperandClass>("ZPR" # RegWidth # "AsmOpndExt" # Repr # Scale # Suffix);
1100 # !if(!eq(RegWidth, 32), "'s'", "'d'") # ">";
1103 foreach RegWidth = [32, 64] in {
1105 def ZPR#RegWidth#AsmOpndExtUXTW8Only : ZPRExtendAsmOperand<"UXTW", RegWidth, 8, 0b1>;
1106 def ZPR#RegWidth#AsmOpndExtUXTW8 : ZPRExtendAsmOperand<"UXTW", RegWidth, 8>;
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| H A D | AArch64ISelDAGToDAG.cpp | 316 template<unsigned RegWidth>
318 return SelectCVTFixedPosOperand(N, FixedPos, RegWidth); in SelectCVTFixedPosOperand()
2855 unsigned RegWidth) { in SelectCVTFixedPosOperand() argument
2891 if (FBits == 0 || FBits > RegWidth) return false; in SelectCVTFixedPosOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 809 inline static bool isAnyMOVZMovAlias(uint64_t Value, int RegWidth) { in isAnyMOVZMovAlias() argument
810 for (int Shift = 0; Shift <= RegWidth - 16; Shift += 16) in isAnyMOVZMovAlias()
817 inline static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth) { in isMOVZMovAlias() argument
818 if (RegWidth == 32) in isMOVZMovAlias()
828 inline static bool isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth) { in isMOVNMovAlias() argument
830 if (isAnyMOVZMovAlias(Value, RegWidth)) in isMOVNMovAlias()
834 if (RegWidth == 32) in isMOVNMovAlias()
837 return isMOVZMovAlias(Value, Shift, RegWidth); in isMOVNMovAlias()
840 inline static bool isAnyMOVWMovAlias(uint64_t Value, int RegWidth) { in isAnyMOVWMovAlias() argument
841 if (isAnyMOVZMovAlias(Value, RegWidth)) in isAnyMOVWMovAlias()
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| H A D | AArch64InstPrinter.cpp | 238 int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32; in printInst() local
245 << formatImm(SignExtend64(Value, RegWidth)); in printInst()
252 int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32; in printInst() local
255 if (RegWidth == 32) in printInst()
258 if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) { in printInst()
260 << formatImm(SignExtend64(Value, RegWidth)); in printInst()
269 int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32; in printInst() local
271 MI->getOperand(2).getImm(), RegWidth); in printInst()
272 if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) { in printInst()
274 << formatImm(SignExtend64(Value, RegWidth)); in printInst()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonTargetTransformInfo.cpp | 177 unsigned RegWidth = in getMemoryOpCost() local
180 assert(RegWidth && "Non-zero vector register width expected"); in getMemoryOpCost()
182 if (VecWidth % RegWidth == 0) in getMemoryOpCost()
183 return VecWidth / RegWidth; in getMemoryOpCost()
185 const Align RegAlign(RegWidth / 8); in getMemoryOpCost()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 1153 void usesRegister(RegisterKind RegKind, unsigned DwordRegIndex, unsigned RegWidth) { in usesRegister() argument
1155 case IS_SGPR: usesSgprAt(DwordRegIndex + RegWidth - 1); break; in usesRegister()
1157 case IS_VGPR: usesVgprAt(DwordRegIndex + RegWidth - 1); break; in usesRegister()
1231 bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth,
1234 unsigned &RegNum, unsigned &RegWidth,
1237 unsigned &RegNum, unsigned &RegWidth,
1240 unsigned &RegWidth,
1243 unsigned &RegWidth,
1246 unsigned &RegWidth, SmallVectorImpl<AsmToken> &Tokens);
1250 unsigned RegWidth,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1009 template<int RegWidth, int Shift>
1017 return AArch64_AM::isMOVZMovAlias(Value, Shift, RegWidth); in isMOVZMovAlias()
1024 template<int RegWidth, int Shift>
1032 return AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth); in isMOVNMovAlias()
4796 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
4799 RegWidth = 64; in MatchAndEmitInstruction()
4801 RegWidth = 32; in MatchAndEmitInstruction()
4803 if (LSB >= RegWidth) in MatchAndEmitInstruction()
4806 if (Width < 1 || Width > RegWidth) in MatchAndEmitInstruction()
4811 if (RegWidth == 32) in MatchAndEmitInstruction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 1044 const unsigned RegWidth = AMDGPU::getRegBitWidth(RC->getID()) / 8; in buildSpillLoadStore() local
1048 unsigned EltSize = (IsFlat && !IsAGPR) ? std::min(RegWidth, 16u) : 4u; in buildSpillLoadStore()
1049 unsigned NumSubRegs = RegWidth / EltSize; in buildSpillLoadStore()
1051 unsigned RemSize = RegWidth - Size; in buildSpillLoadStore()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 1489 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); in getNumRegisters() local
1490 return (BitWidth + RegWidth - 1) / RegWidth; in getNumRegisters()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | CodeGenPrepare.cpp | 6978 unsigned RegWidth = RegType.getSizeInBits(); in optimizeSwitchInst() local
6980 if (RegWidth <= cast<IntegerType>(OldType)->getBitWidth()) in optimizeSwitchInst()
6989 auto *NewType = Type::getIntNTy(Context, RegWidth); in optimizeSwitchInst()
7007 NarrowConst.zext(RegWidth) : NarrowConst.sext(RegWidth); in optimizeSwitchInst()
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