| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/MCTargetDesc/ |
| H A D | LanaiInstPrinter.cpp | 214 const MCOperand &RegOp) { in printMemoryBaseRegister() argument
215 assert(RegOp.isReg() && "Register operand expected"); in printMemoryBaseRegister()
219 OS << "%" << LanaiInstPrinter::getRegisterName(RegOp.getReg()); in printMemoryBaseRegister()
240 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemRiOperand() local
249 printMemoryBaseRegister(OS, AluCode, RegOp); in printMemRiOperand()
255 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemRrOperand() local
259 assert(OffsetOp.isReg() && RegOp.isReg() && "Registers expected."); in printMemRrOperand()
265 OS << "%" << getRegisterName(RegOp.getReg()); in printMemRrOperand()
276 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemSplsOperand() local
285 printMemoryBaseRegister(OS, AluCode, RegOp); in printMemSplsOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 528 inline unsigned getRegState(const MachineOperand &RegOp) { in getRegState() argument
529 assert(RegOp.isReg() && "Not a register operand"); in getRegState()
530 return getDefRegState(RegOp.isDef()) | getImplRegState(RegOp.isImplicit()) | in getRegState()
531 getKillRegState(RegOp.isKill()) | getDeadRegState(RegOp.isDead()) | in getRegState()
532 getUndefRegState(RegOp.isUndef()) | in getRegState()
533 getInternalReadRegState(RegOp.isInternalRead()) | in getRegState()
534 getDebugRegState(RegOp.isDebug()) | in getRegState()
535 getRenamableRegState(Register::isPhysicalRegister(RegOp.getReg()) && in getRegState()
536 RegOp.isRenamable()); in getRegState()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/MCTargetDesc/ |
| H A D | BPFInstPrinter.cpp | 67 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemOperand() local
71 assert(RegOp.isReg() && "Register operand not a register"); in printMemOperand()
72 O << getRegisterName(RegOp.getReg()); in printMemOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrFoldTables.h | 86 const X86MemoryFoldTableEntry *lookupTwoAddrFoldTable(unsigned RegOp);
90 const X86MemoryFoldTableEntry *lookupFoldTable(unsigned RegOp, unsigned OpNum);
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| H A D | X86MCInstLower.cpp | 378 unsigned RegOp = IsStore ? 0 : 5; in SimplifyShortMoveForm() local
381 Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && in SimplifyShortMoveForm()
390 unsigned Reg = Inst.getOperand(RegOp).getReg(); in SimplifyShortMoveForm()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| H A D | AVRAsmPrinter.cpp | 99 const MachineOperand &RegOp = MI->getOperand(OpNum); in PrintAsmOperand() local
101 assert(RegOp.isReg() && "Operand must be a register when you're" in PrintAsmOperand()
103 Register Reg = RegOp.getReg(); in PrintAsmOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| H A D | LanaiAsmPrinter.cpp | 130 unsigned RegOp = OpNo + 1; in PrintAsmOperand() local
131 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
133 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/MCTargetDesc/ |
| H A D | AVRMCCodeEmitter.cpp | 137 auto RegOp = MI.getOperand(OpNo); in encodeMemri() local
140 assert(RegOp.isReg() && "Expected register operand"); in encodeMemri()
144 switch (RegOp.getReg()) { in encodeMemri()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsAsmPrinter.cpp | 586 unsigned RegOp = OpNum; in PrintAsmOperand() local
592 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum; in PrintAsmOperand()
595 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1; in PrintAsmOperand()
598 RegOp = OpNum + 1; in PrintAsmOperand()
600 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
602 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 1431 const MachineOperand *RegOp = nullptr; in isOMod() local
1437 RegOp = Src1; in isOMod()
1440 RegOp = Src0; in isOMod()
1452 return std::make_pair(RegOp, OMod); in isOMod()
1484 const MachineOperand *RegOp; in tryFoldOMod() local
1486 std::tie(RegOp, OMod) = isOMod(MI); in tryFoldOMod()
1487 if (OMod == SIOutMods::NONE || !RegOp->isReg() || in tryFoldOMod()
1488 RegOp->getSubReg() != AMDGPU::NoSubRegister || in tryFoldOMod()
1489 !MRI->hasOneNonDBGUser(RegOp->getReg())) in tryFoldOMod()
1492 MachineInstr *Def = MRI->getVRegDef(RegOp->getReg()); in tryFoldOMod()
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| H A D | SIInstrInfo.cpp | 1098 MachineOperand RegOp = Cond[1]; in insertVectorSelect() local
1099 RegOp.setImplicit(false); in insertVectorSelect()
1102 .add(RegOp); in insertVectorSelect()
1112 MachineOperand RegOp = Cond[1]; in insertVectorSelect() local
1113 RegOp.setImplicit(false); in insertVectorSelect()
1116 .add(RegOp); in insertVectorSelect()
2041 MachineOperand &RegOp, in swapRegAndNonRegOperand() argument
2043 Register Reg = RegOp.getReg(); in swapRegAndNonRegOperand()
2044 unsigned SubReg = RegOp.getSubReg(); in swapRegAndNonRegOperand()
2045 bool IsKill = RegOp.isKill(); in swapRegAndNonRegOperand()
[all …]
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| H A D | AMDGPUMachineCFGStructurizer.cpp | 1860 MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true); in createIfBlock() local
1861 ArrayRef<MachineOperand> Cond(RegOp); in createIfBlock()
2319 MachineOperand RegOp = in createIfRegion() local
2321 ArrayRef<MachineOperand> Cond(RegOp); in createIfRegion()
2378 MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true); in createIfRegion() local
2379 ArrayRef<MachineOperand> Cond(RegOp); in createIfRegion()
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| H A D | GCNHazardRecognizer.cpp | 142 const MachineOperand *RegOp = TII->getNamedOperand(RegInstr, in getHWReg() local
144 return RegOp->getImm() & AMDGPU::Hwreg::ID_MASK_; in getHWReg()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/AsmParser/ |
| H A D | BPFAsmParser.cpp | 89 struct RegOp { struct
100 RegOp Reg;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 287 Register RegOp = VisitedPHI->getOperand(PHIOp).getReg(); in collectUnprimedAccPHIs() local
288 if (!Register::isVirtualRegister(RegOp)) in collectUnprimedAccPHIs()
290 MachineInstr *Instr = MRI->getVRegDef(RegOp); in collectUnprimedAccPHIs()
334 Register RegOp = PHI->getOperand(PHIOp).getReg(); in convertUnprimedAccPHIs() local
335 MachineInstr *PHIInput = MRI->getVRegDef(RegOp); in convertUnprimedAccPHIs()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/CSKY/AsmParser/ |
| H A D | CSKYAsmParser.cpp | 90 struct RegOp { struct
101 RegOp Reg;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86Operand.h | 44 struct RegOp { struct
74 struct RegOp Reg;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCCodeEmitter.cpp | 1641 unsigned RegOp = CurOp++; in encodeInstruction() local
1648 emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(RegOp)), in encodeInstruction()
1654 unsigned RegOp = CurOp++; in encodeInstruction() local
1658 emitRegModRMByte(MI.getOperand(RegOp), 0, OS); in encodeInstruction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 395 MachineOperand &RegOp = PI.getOperand(i); in preprocessPhiNodes() local
396 if (RegOp.getSubReg() == 0) in preprocessPhiNodes()
406 .addReg(RegOp.getReg(), getRegState(RegOp), in preprocessPhiNodes()
407 RegOp.getSubReg()); in preprocessPhiNodes()
409 RegOp.setReg(NewReg); in preprocessPhiNodes()
410 RegOp.setSubReg(0); in preprocessPhiNodes()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/AsmParser/ |
| H A D | LanaiAsmParser.cpp | 122 struct RegOp { struct
139 struct RegOp Reg;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMAsmPrinter.cpp | 398 unsigned RegOp = FirstHalf ? OpNum : OpNum + 1; in PrintAsmOperand() local
399 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
401 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 814 MachineOperand &RegOp = I.getOperand(1); in copySubReg() local
815 RegOp.setReg(SubRegCopy.getReg(0)); in copySubReg()
941 MachineOperand &RegOp = I.getOperand(1); in selectCopy() local
942 RegOp.setReg(PromoteReg); in selectCopy()
2430 MachineOperand &RegOp = I.getOperand(0); in select() local
2431 RegOp.setReg(DefGPRReg); in select()
4887 MachineOperand &RegOp = I.getOperand(1); in selectBuildVector() local
4888 RegOp.setReg(Reg); in selectBuildVector()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 237 struct RegOp { struct in __anon6f8db8bd0211::SparcOperand
254 struct RegOp Reg;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 105 struct RegOp { struct in __anond0f948490111::SystemZOperand
135 RegOp Reg;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/AsmParser/ |
| H A D | VEAsmParser.cpp | 172 struct RegOp { struct in __anonf0f8b3610211::VEOperand
202 struct RegOp Reg;
|