| /netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/ |
| H A D | RegisterFile.cpp | 109 MCPhysReg RegID = WS.getRegisterID(); in onInstructionExecuted() local
110 assert(RegID != 0 && "A write of an invalid register?"); in onInstructionExecuted()
115 MCPhysReg RenameAs = RegisterMappings[RegID].second.RenameAs; in onInstructionExecuted()
116 if (RenameAs && RenameAs != RegID) in onInstructionExecuted()
117 RegID = RenameAs; in onInstructionExecuted()
119 WriteRef &WR = RegisterMappings[RegID].first; in onInstructionExecuted()
123 for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I) { in onInstructionExecuted()
132 for (MCSuperRegIterator I(RegID, &MRI); I.isValid(); ++I) { in onInstructionExecuted()
224 MCPhysReg RegID = WS.getRegisterID(); in addRegisterWrite() local
225 assert(RegID && "Adding an invalid register definition?"); in addRegisterWrite()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/ |
| H A D | Instruction.cpp | 21 void WriteState::writeStartEvent(unsigned IID, MCPhysReg RegID, in writeStartEvent() argument
24 CRD.RegID = RegID; in writeStartEvent()
30 void ReadState::writeStartEvent(unsigned IID, MCPhysReg RegID, in writeStartEvent() argument
43 CRD.RegID = RegID; in writeStartEvent()
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| H A D | InstrBuilder.cpp | 636 MCPhysReg RegID = 0; in createInstruction() local
644 RegID = Op.getReg(); in createInstruction()
647 RegID = RD.RegisterID; in createInstruction()
651 if (!RegID) in createInstruction()
655 NewIS->getUses().emplace_back(RD, RegID); in createInstruction()
695 RegID = WD.isImplicitWrite() ? WD.RegisterID in createInstruction()
698 if (WD.IsOptionalDef && !RegID) { in createInstruction()
703 assert(RegID && "Expected a valid register ID!"); in createInstruction()
704 NewIS->getDefs().emplace_back(WD, RegID, in createInstruction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MCA/ |
| H A D | Instruction.h | 89 MCPhysReg RegID; member
150 WriteState(const WriteDescriptor &Desc, MCPhysReg RegID,
152 : WD(&Desc), CyclesLeft(UNKNOWN_CYCLES), RegisterID(RegID), PRFID(0),
204 void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles);
257 ReadState(const ReadDescriptor &Desc, MCPhysReg RegID) in ReadState() argument
258 : RD(&Desc), RegisterID(RegID), PRFID(0), DependentWrites(0), in ReadState()
276 void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles);
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| /netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-mca/Views/ |
| H A D | BottleneckAnalysis.h | 252 void addRegisterDep(unsigned From, unsigned To, unsigned RegID, in addRegisterDep() argument
254 addDependency(From, To, {DependencyEdge::DT_REGISTER, RegID, Cost}); in addRegisterDep()
314 void addRegisterDep(unsigned From, unsigned To, unsigned RegID, unsigned Cy);
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| H A D | BottleneckAnalysis.cpp | 454 unsigned RegID, unsigned Cost) { in addRegisterDep() argument
458 DG.addRegisterDep(From, To + SourceSize, RegID, Cost); in addRegisterDep()
459 DG.addRegisterDep(From + SourceSize, To + (SourceSize * 2), RegID, Cost); in addRegisterDep()
462 DG.addRegisterDep(From + SourceSize, To + SourceSize, RegID, Cost); in addRegisterDep()
523 addRegisterDep(From, To, RegDep.RegID, Cycles); in onEvent()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCTargetDesc.cpp | 432 auto ClearsSuperReg = [=](unsigned RegID) { in clearsSuperRegisters() argument
437 if (GR32RC.contains(RegID)) in clearsSuperRegisters()
448 return VR128XRC.contains(RegID) || VR256XRC.contains(RegID); in clearsSuperRegisters()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 6417 auto RegID = IntrinsicID == Intrinsic::amdgcn_dispatch_ptr ? in LowerINTRINSIC_WO_CHAIN() local
6419 return getPreloadedValue(DAG, *MFI, VT, RegID); in LowerINTRINSIC_WO_CHAIN()
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