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Searched refs:RegClass (Results 1 – 25 of 69) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVVLPatterns.td303 vti.LMul, vti.RegClass, vti.RegClass>;
306 vti.LMul, vti.RegClass, vti.RegClass,
317 vti.LMul, vti.RegClass, vti.RegClass,
346 vti.LMul, vti.RegClass, vti.RegClass>;
349 vti.LMul, vti.RegClass, vti.RegClass,
357 fvti.RegClass:$rs1,
361 fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2,
367 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
368 vti.RegClass:$rs2, cc,
372 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl,
[all …]
H A DRISCVInstrInfoVSDPatterns.td145 vti.LMul, vti.AVL, vti.RegClass, vti.RegClass>;
148 vti.LMul, vti.AVL, vti.RegClass, vti.RegClass,
159 vti.LMul, vti.AVL, vti.RegClass, vti.RegClass,
188 vti.LMul, vti.AVL, vti.RegClass, vti.RegClass>;
191 vti.Log2SEW, vti.LMul, vti.AVL, vti.RegClass, vti.RegClass,
199 (fvti.Vector fvti.RegClass:$rs1))),
201 fvti.RegClass:$rs1,
211 def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
212 (vti.Vector vti.RegClass:$rs2), cc)),
214 (instruction vti.RegClass:$rs1),
[all …]
H A DRISCVInstrInfoVPseudos.td152 VReg RegClass = Reg;
800 class VPseudoNullaryNoMask<VReg RegClass>:
801 Pseudo<(outs RegClass:$rd),
815 class VPseudoNullaryMask<VReg RegClass>:
816 Pseudo<(outs GetVRegNoV0<RegClass>.R:$rd),
817 (ins GetVRegNoV0<RegClass>.R:$merge, VMaskOp:$vm, AVL:$vl,
2418 vti.Log2SEW, vti.LMul, vti.RegClass,
2419 vti.RegClass>;
2438 vti.Mask, vti.Log2SEW, vti.LMul, vti.RegClass, VR>;
2451 vti.Log2SEW, vti.LMul, fti.RegClass>;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
H A DRegisterAliasing.cpp33 const MCRegisterClass &RegClass) in RegisterAliasingTracker() argument
35 for (MCPhysReg PhysReg : RegClass) in RegisterAliasingTracker()
76 const auto &RegClass = RegInfo.getRegClass(RegClassIndex); in getRegisterClass() local
78 Found.reset(new RegisterAliasingTracker(RegInfo, ReservedReg, RegClass)); in getRegisterClass()
H A DMCInstrDescView.cpp119 if (OpInfo.RegClass >= 0) in create()
120 Operand.Tracker = &RATC.getRegisterClass(OpInfo.RegClass); in create()
274 &RegInfo.getRegClass(Op.Info->RegClass)) in dump()
H A DRegisterAliasing.h45 const MCRegisterClass &RegClass);
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRInstPrinter.cpp104 if (MOI.RegClass == AVR::ZREGRegClassID) { in printOperand()
124 bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) || in printOperand()
125 (MOI.RegClass == AVR::PTRDISPREGSRegClassID) || in printOperand()
126 (MOI.RegClass == AVR::ZREGRegClassID); in printOperand()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DRDFRegisters.cpp36 if (RI.RegClass != nullptr && !BadRC[R]) { in PhysicalRegisterInfo()
37 if (RC->LaneMask != RI.RegClass->LaneMask) { in PhysicalRegisterInfo()
39 RI.RegClass = nullptr; in PhysicalRegisterInfo()
42 RI.RegClass = RC; in PhysicalRegisterInfo()
66 if (const TargetRegisterClass *RC = RegInfos[F].RegClass) in PhysicalRegisterInfo()
176 const TargetRegisterClass *RC = RegInfos[RR.Reg].RegClass; in aliasRM()
237 LaneBitmask RCM = RI.RegClass ? RI.RegClass->LaneMask in mapTo()
H A DRegisterClassInfo.cpp50 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
94 RCInfo &RCI = RegClass[RC->getID()]; in compute()
H A DMachineRegisterInfo.cpp158 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, in createVirtualRegister() argument
160 assert(RegClass && "Cannot create register without RegClass!"); in createVirtualRegister()
161 assert(RegClass->isAllocatable() && in createVirtualRegister()
166 VRegInfo[Reg].first = RegClass; in createVirtualRegister()
H A DRenameIndependentSubregs.cpp134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in INITIALIZE_PASS_DEPENDENCY() local
142 Register NewVReg = MRI->createVirtualRegister(RegClass); in INITIALIZE_PASS_DEPENDENCY()
H A DTargetInstrInfo.cpp53 short RegClass = MCID.OpInfo[OpNum].RegClass; in getRegClass() local
55 return TRI->getPointerRegClass(MF, RegClass); in getRegClass()
58 if (RegClass < 0) in getRegClass()
62 return TRI->getRegClass(RegClass); in getRegClass()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrArithmetic.td552 /// RegClass - This is the register class associated with this type. For
554 RegisterClass RegClass = regclass;
644 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
654 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
660 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), WriteALU,
661 [(set typeinfo.RegClass:$dst, EFLAGS,
662 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
668 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), WriteADC,
669 [(set typeinfo.RegClass:$dst, EFLAGS,
670 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2,
[all …]
H A DX86FrameLowering.cpp797 const TargetRegisterClass *RegClass = &X86::GR64RegClass; in emitStackProbeInlineWindowsCoreCLR64() local
799 : MRI.createVirtualRegister(RegClass), in emitStackProbeInlineWindowsCoreCLR64()
801 : MRI.createVirtualRegister(RegClass), in emitStackProbeInlineWindowsCoreCLR64()
803 : MRI.createVirtualRegister(RegClass), in emitStackProbeInlineWindowsCoreCLR64()
805 : MRI.createVirtualRegister(RegClass), in emitStackProbeInlineWindowsCoreCLR64()
807 : MRI.createVirtualRegister(RegClass), in emitStackProbeInlineWindowsCoreCLR64()
809 : MRI.createVirtualRegister(RegClass), in emitStackProbeInlineWindowsCoreCLR64()
811 : MRI.createVirtualRegister(RegClass), in emitStackProbeInlineWindowsCoreCLR64()
813 : MRI.createVirtualRegister(RegClass), in emitStackProbeInlineWindowsCoreCLR64()
815 : MRI.createVirtualRegister(RegClass); in emitStackProbeInlineWindowsCoreCLR64()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegStackify.cpp106 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); in convertImplicitDefToConstZero() local
107 if (RegClass == &WebAssembly::I32RegClass) { in convertImplicitDefToConstZero()
110 } else if (RegClass == &WebAssembly::I64RegClass) { in convertImplicitDefToConstZero()
113 } else if (RegClass == &WebAssembly::F32RegClass) { in convertImplicitDefToConstZero()
118 } else if (RegClass == &WebAssembly::F64RegClass) { in convertImplicitDefToConstZero()
123 } else if (RegClass == &WebAssembly::V128RegClass) { in convertImplicitDefToConstZero()
639 const auto *RegClass = MRI.getRegClass(Reg); in moveAndTeeForMultiUse() local
640 Register TeeReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse()
641 Register DefReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse()
644 TII->get(getTeeOpcode(RegClass)), TeeReg) in moveAndTeeForMultiUse()
H A DWebAssemblyPeephole.cpp97 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough() local
98 switch (RegClass->getID()) { in maybeRewriteToFallthrough()
123 Register NewReg = MRI.createVirtualRegister(RegClass); in maybeRewriteToFallthrough()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp41 const TargetRegisterClass &RegClass) { in constrainRegToClass() argument
42 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) in constrainRegToClass()
43 return MRI.createVirtualRegister(&RegClass); in constrainRegToClass()
52 const TargetRegisterClass &RegClass, MachineOperand &RegMO) { in constrainOperandRegClass() argument
57 Register ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass); in constrainOperandRegClass()
102 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); in constrainOperandRegClass() local
111 if (RegClass && !RegClass->isAllocatable()) in constrainOperandRegClass()
112 RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI); in constrainOperandRegClass()
114 if (!RegClass) { in constrainOperandRegClass()
130 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass, in constrainOperandRegClass()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h47 std::unique_ptr<RCInfo[]> RegClass; variable
77 const RCInfo &RCI = RegClass[RC->getID()]; in get()
H A DRegisterScavenging.h157 Register scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj,
159 return scavengeRegister(RegClass, MBBI, SPAdj, AllowSpill);
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h88 const TargetRegisterClass &RegClass);
104 const TargetRegisterClass &RegClass,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUMachineCFGStructurizer.cpp1912 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectReg); in rewriteCodeBBTerminator() local
1913 Register TrueBBReg = MRI->createVirtualRegister(RegClass); in rewriteCodeBBTerminator()
1914 Register FalseBBReg = MRI->createVirtualRegister(RegClass); in rewriteCodeBBTerminator()
1979 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg); in insertChainedPHI() local
1980 Register NextDestReg = MRI->createVirtualRegister(RegClass); in insertChainedPHI()
2039 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in rewriteLiveOutRegs() local
2040 Register PHIDestReg = MRI->createVirtualRegister(RegClass); in rewriteLiveOutRegs()
2041 Register IfSourceReg = MRI->createVirtualRegister(RegClass); in rewriteLiveOutRegs()
2154 const TargetRegisterClass *RegClass = in createEntryPHI() local
2156 Register NewBackedgeReg = MRI->createVirtualRegister(RegClass); in createEntryPHI()
[all …]
H A DSIInstrInfo.cpp988 const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg); in materializeImmediate() local
989 if (RegClass == &AMDGPU::SReg_32RegClass || in materializeImmediate()
990 RegClass == &AMDGPU::SGPR_32RegClass || in materializeImmediate()
991 RegClass == &AMDGPU::SReg_32_XM0RegClass || in materializeImmediate()
992 RegClass == &AMDGPU::SReg_32_XM0_XEXECRegClass) { in materializeImmediate()
998 if (RegClass == &AMDGPU::SReg_64RegClass || in materializeImmediate()
999 RegClass == &AMDGPU::SGPR_64RegClass || in materializeImmediate()
1000 RegClass == &AMDGPU::SReg_64_XEXECRegClass) { in materializeImmediate()
1006 if (RegClass == &AMDGPU::VGPR_32RegClass) { in materializeImmediate()
1011 if (RegClass->hasSuperClassEq(&AMDGPU::VReg_64RegClass)) { in materializeImmediate()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DRISCVCompressInstEmitter.cpp121 bool validateRegister(Record *Reg, Record *RegClass);
141 bool RISCVCompressInstEmitter::validateRegister(Record *Reg, Record *RegClass) { in validateRegister() argument
143 assert(RegClass->isSubClassOf("RegisterClass") && in validateRegister()
145 const CodeGenRegisterClass &RC = Target.getRegisterClass(RegClass); in validateRegister()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp528 const TargetRegisterClass *RegClass = in rewriteT2FrameIndex() local
709 RegClass->contains(FrameReg))) { in rewriteT2FrameIndex()
713 if (!MRI->constrainRegClass(FrameReg, RegClass)) in rewriteT2FrameIndex()
750 RegClass->contains(FrameReg)); in rewriteT2FrameIndex()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64LoadStoreOptimizer.cpp1356 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); in canRenameUpToDef() local
1358 if (!RegClass || !MF.getRegInfo().tracksLiveness()) in canRenameUpToDef()
1375 auto *RegClass = TRI->getMinimalPhysRegClass(MOP.getReg()); in canRenameUpToDef() local
1382 if (RegClass->HasDisjunctSubRegs) { in canRenameUpToDef()
1502 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); in tryToFindRegisterToRename() local
1503 for (const MCPhysReg &PR : *RegClass) { in tryToFindRegisterToRename()
1514 << TRI->getRegClassName(RegClass) << "\n"); in tryToFindRegisterToRename()

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