| /netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | RegisterInfoEmitter.cpp | 62 CodeGenRegBank &RegBank = Target.getRegBank(); in RegisterInfoEmitter() local
63 RegBank.computeDerivedInfo(); in RegisterInfoEmitter()
91 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
93 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
95 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
208 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, in EmitRegUnitPressure() argument
210 unsigned NumRCs = RegBank.getRegClasses().size(); in EmitRegUnitPressure()
211 unsigned NumSets = RegBank.getNumRegPressureSets(); in EmitRegUnitPressure()
217 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure()
219 OS << " {" << RC.getWeight(RegBank) << ", "; in EmitRegUnitPressure()
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| H A D | CodeGenRegisters.cpp | 76 void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) { in updateComponents() argument
85 CodeGenSubRegIndex *A = RegBank.getSubRegIdx(Comps[0]); in updateComponents()
86 CodeGenSubRegIndex *B = RegBank.getSubRegIdx(Comps[1]); in updateComponents()
100 IdxParts.push_back(RegBank.getSubRegIdx(Part)); in updateComponents()
165 void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) { in buildObjectGraph() argument
174 ExplicitSubRegIndices.push_back(RegBank.getSubRegIdx(SRIs[i])); in buildObjectGraph()
175 ExplicitSubRegs.push_back(RegBank.getReg(SRs[i])); in buildObjectGraph()
190 CodeGenRegister *Reg = RegBank.getReg(Alias); in buildObjectGraph()
252 bool CodeGenRegister::inheritRegUnits(CodeGenRegBank &RegBank) { in inheritRegUnits() argument
264 CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) { in computeSubRegs() argument
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| H A D | CodeGenTarget.h | 53 mutable std::unique_ptr<CodeGenRegBank> RegBank; variable
113 getSuperRegForSubReg(const ValueTypeByHwMode &Ty, CodeGenRegBank &RegBank,
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| H A D | CodeGenRegisters.h | 251 bool inheritRegUnits(CodeGenRegBank &RegBank);
258 unsigned getWeight(const CodeGenRegBank &RegBank) const;
397 getMatchingSubClassWithSubRegs(CodeGenRegBank &RegBank,
448 void buildRegUnitSet(const CodeGenRegBank &RegBank,
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| H A D | CodeGenTarget.cpp | 282 auto &RegClasses = RegBank->getRegClasses(); in getRegNamespace()
336 if (!RegBank) in getRegBank()
337 RegBank = std::make_unique<CodeGenRegBank>(Records, getHwModes()); in getRegBank()
338 return *RegBank; in getRegBank()
343 CodeGenRegBank &RegBank, in getSuperRegForSubReg() argument
347 auto &RegClasses = RegBank.getRegClasses(); in getSuperRegForSubReg()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | RegisterBankInfo.cpp | 72 const RegisterBank &RegBank = getRegBank(Idx); in verify() local
73 assert(Idx == RegBank.getID() && in verify()
75 LLVM_DEBUG(dbgs() << "Verify " << RegBank << '\n'); in verify()
76 assert(RegBank.verify(TRI) && "RegBank is invalid"); in verify()
125 const RegisterBank &RegBank = getRegBankFromRegClass(*RC, MRI.getType(Reg)); in getRegBankFromConstraints() local
127 assert(RegBank.covers(*RC) && in getRegBankFromConstraints()
129 return &RegBank; in getRegBankFromConstraints()
268 const RegisterBank *RegBank) { in hashPartialMapping() argument
269 return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0); in hashPartialMapping()
276 PartMapping.RegBank); in hash_value()
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| H A D | RegBankSelect.cpp | 122 const RegisterBank *DesiredRegBank = ValMapping.BreakDown[0].RegBank; in assignmentMatch()
263 const RegisterBank *DesiredRegBank = ValMapping.BreakDown[0].RegBank; in getRepairCost()
604 MRI->setRegBank(Reg, *ValMapping.BreakDown[0].RegBank); in applyMapping()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | RegisterBankInfo.h | 60 const RegisterBank *RegBank; member
66 const RegisterBank &RegBank) in PartialMapping()
67 : StartIdx(StartIdx), Length(Length), RegBank(&RegBank) {} in PartialMapping()
464 const RegisterBank &RegBank) const;
472 const RegisterBank &RegBank) const;
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| H A D | RegisterBank.h | 92 inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) {
93 RegBank.print(OS);
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 138 unsigned selectLoadStoreOpCode(unsigned Opc, unsigned RegBank,
189 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass() local
190 assert(RegBank && "Can't get reg bank for virtual register"); in guessRegClass()
193 assert((RegBank->getID() == ARM::GPRRegBankID || in guessRegClass()
194 RegBank->getID() == ARM::FPRRegBankID) && in guessRegClass()
197 if (RegBank->getID() == ARM::FPRRegBankID) { in guessRegClass()
356 unsigned RegBank, in selectLoadStoreOpCode() argument
360 if (RegBank == ARM::GPRRegBankID) { in selectLoadStoreOpCode()
374 if (RegBank == ARM::FPRRegBankID) { in selectLoadStoreOpCode()
1087 unsigned RegBank = RBI.getRegBank(Reg, MRI, TRI)->getID(); in select() local
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| H A D | ARMRegisterBankInfo.cpp | 52 PM.RegBank->getID() == RegBankID; in checkPartMapping()
479 (Mapping.RegBank->getID() != ARM::FPRRegBankID || in getInstrMapping()
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| /netbsd-src/external/gpl3/gdb/dist/sim/arm/ |
| H A D | armsupp.c | 44 return (state->RegBank[ModeToBank ((ARMword) mode)][reg]); in ARMul_GetReg()
56 state->RegBank[ModeToBank ((ARMword) mode)][reg] = value; in ARMul_SetReg()
316 state->RegBank[USERBANK][i] = state->Reg[i]; in ARMul_SwitchMode()
317 state->RegBank[oldbank][13] = state->Reg[13]; in ARMul_SwitchMode()
318 state->RegBank[oldbank][14] = state->Reg[14]; in ARMul_SwitchMode()
322 state->RegBank[FIQBANK][i] = state->Reg[i]; in ARMul_SwitchMode()
326 state->RegBank[DUMMYBANK][i] = 0; in ARMul_SwitchMode()
342 state->Reg[i] = state->RegBank[USERBANK][i]; in ARMul_SwitchMode()
343 state->Reg[13] = state->RegBank[newbank][13]; in ARMul_SwitchMode()
344 state->Reg[14] = state->RegBank[newbank][14]; in ARMul_SwitchMode()
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| H A D | arminit.c | 93 state->RegBank[j][i] = 0; in ARMul_NewState()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 264 ValMapping.BreakDown[0].RegBank == ValMapping.BreakDown[1].RegBank); in getBreakDownCost()
1148 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; in applyMappingLoad()
1425 OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank; in applyMappingSBufferLoad()
1427 OpdMapper.getInstrMapping().getOperandMapping(2).BreakDown[0].RegBank; in applyMappingSBufferLoad()
1548 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; in applyMappingBFEIntrinsic()
1877 const RegisterBank &RegBank, in extendLow32IntoHigh32() argument
1889 B.getMRI()->setRegBank(ShiftAmt.getReg(0), RegBank); in extendLow32IntoHigh32()
1906 *OpdMapper.getInstrMapping().getOperandMapping(2).BreakDown[0].RegBank; in foldExtractEltToCmpSelect()
1922 *OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; in foldExtractEltToCmpSelect()
1924 *OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank; in foldExtractEltToCmpSelect()
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| H A D | AMDGPUGenRegisterBankInfo.def | 46 // StartIdx, Length, RegBank
196 assert(BankID == ValMappings[Idx].BreakDown->RegBank->getID());
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIRParser.cpp | 562 Info.D.RegBank = nullptr; in parseRegisterInfo()
569 const RegisterBank *RegBank = Target->getRegBank(VReg.Class.Value); in parseRegisterInfo() local
570 if (!RegBank) in parseRegisterInfo()
576 Info.D.RegBank = RegBank; in parseRegisterInfo()
645 MRI.setRegBank(Reg, *Info.D.RegBank); in setupRegisterInfo()
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| H A D | MIParser.cpp | 298 const auto &RegBank = RBI->getRegBank(I); in initNames2RegBanks() local
300 std::make_pair(StringRef(RegBank.getName()).lower(), &RegBank)); in initNames2RegBanks()
1358 const RegisterBank *RegBank = nullptr; in parseRegisterClassOrBank() local
1360 RegBank = PFS.Target.getRegBank(Name); in parseRegisterClassOrBank()
1361 if (!RegBank) in parseRegisterClassOrBank()
1371 RegInfo.Kind = RegBank ? VRegInfo::REGBANK : VRegInfo::GENERIC; in parseRegisterClassOrBank()
1372 if (RegInfo.Explicit && RegInfo.D.RegBank != RegBank) in parseRegisterClassOrBank()
1374 RegInfo.D.RegBank = RegBank; in parseRegisterClassOrBank()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86GenRegisterBankInfo.def | 15 /* StartIdx, Length, RegBank */
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| H A D | X86InstructionSelector.cpp | 200 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass() local
201 return getRegClass(Ty, RegBank); in getRegClass()
1323 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectMergeValues() local
1327 MRI.setRegBank(DefReg, RegBank); in selectMergeValues()
1333 MRI.setRegBank(Tmp, RegBank); in selectMergeValues()
1392 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); in materializeFP() local
1397 getLoadStoreOp(DstTy, RegBank, TargetOpcode::G_LOAD, Alignment); in materializeFP()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64GenRegisterBankInfo.def | 15 /* StartIdx, Length, RegBank */
131 Map.RegBank == &RB;
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/MIRParser/ |
| H A D | MIParser.h | 42 const RegisterBank *RegBank; member
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | MachineRegisterInfo.cpp | 64 const RegisterBank &RegBank) { in setRegBank() argument
65 VRegInfo[Reg].first = &RegBank; in setRegBank()
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| H A D | MachineVerifier.cpp | 1947 const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg); in visitMachineOperand() local
1950 if (!RegBank && isFunctionRegBankSelected) { in visitMachineOperand()
1958 if (RegBank && Ty.isValid() && in visitMachineOperand()
1959 RegBank->getSize() < Ty.getSizeInBits()) { in visitMachineOperand()
1962 errs() << "Register bank " << RegBank->getName() << " too small(" in visitMachineOperand()
1963 << RegBank->getSize() << ") to fit " << Ty.getSizeInBits() in visitMachineOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 738 *AArch64GenRegisterBankInfo::PartMappings[OpRegBankIdx[0]].RegBank, in getInstrMapping()
739 *AArch64GenRegisterBankInfo::PartMappings[OpRegBankIdx[1]].RegBank, in getInstrMapping()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | MachineRegisterInfo.h | 676 void setRegBank(Register Reg, const RegisterBank &RegBank);
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