| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 560 bool isSubRegister(MCRegister RegA, MCRegister RegB) const { in isSubRegister() argument
561 return isSuperRegister(RegB, RegA); in isSubRegister()
565 bool isSuperRegister(MCRegister RegA, MCRegister RegB) const;
568 bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSubRegisterEq() argument
569 return isSuperRegisterEq(RegB, RegA); in isSubRegisterEq()
574 bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSuperRegisterEq() argument
575 return RegA == RegB || isSuperRegister(RegA, RegB); in isSuperRegisterEq()
580 bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSuperOrSubRegisterEq() argument
581 return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB); in isSuperOrSubRegisterEq()
656 inline bool MCRegisterInfo::isSuperRegister(MCRegister RegA, MCRegister RegB) const{ in isSuperRegister() argument
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TwoAddressInstructionPass.cpp | 125 bool isProfitableToCommute(Register RegA, Register RegB, Register RegC,
131 bool isProfitableToConv3Addr(Register RegA, Register RegB);
135 Register RegB, unsigned Dist);
416 static bool regsAreCompatible(Register RegA, Register RegB, in regsAreCompatible() argument
418 if (RegA == RegB) in regsAreCompatible()
420 if (!RegA || !RegB) in regsAreCompatible()
422 return TRI->regsOverlap(RegA, RegB); in regsAreCompatible()
438 Register RegB, in isProfitableToCommute() argument
478 MCRegister FromRegB = getMappedReg(RegB, SrcRegMap); in isProfitableToCommute()
506 if (!noUseAfterLastDef(RegB, Dist, LastDefB)) in isProfitableToCommute()
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| H A D | ImplicitNullChecks.cpp | 293 Register RegB = MOB.getReg(); in canReorder() local
295 if (TRI->regsOverlap(RegA, RegB) && (MOA.isDef() || MOB.isDef())) in canReorder()
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| H A D | TargetInstrInfo.cpp | 845 Register RegB = OpB.getReg(); in reassociateOps() local
852 if (Register::isVirtualRegister(RegB)) in reassociateOps()
853 MRI.constrainRegClass(RegB, RC); in reassociateOps()
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| /netbsd-src/external/gpl3/binutils.old/dist/opcodes/ |
| H A D | i386-opc.h | 801 RegB, /* %bl / %bx / %ebx / %rbx */ enumerator
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| H A D | i386-reg.tbl | 67 ebx, Class=Reg|Instance=RegB|Dword|BaseIndex, 0, 3, 3, Dw2Inval
83 rbx, Class=Reg|Instance=RegB|Qword|BaseIndex, 0, 3, Dw2Inval, 3
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| H A D | ChangeLog-2019 | 484 * i386-gen.c (operand_instances): Add RegB entry.
485 * i386-opc.h (enum operand_instance): Add RegB.
486 * i386-opc.tbl (RegC, RegD, RegB): Define.
493 (ebx, rbx): Add Instance=RegB.
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| H A D | i386-gen.c | 769 INSTANCE (RegB),
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| H A D | i386-opc.tbl | 37 #define RegB Instance=RegB
3321 …f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Acc|Dword|Qword, RegC|Dword|Qword, RegB|Dword|Qword }
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| /netbsd-src/external/gpl3/binutils/dist/opcodes/ |
| H A D | i386-opc.h | 831 RegB, /* %bl / %bx / %ebx / %rbx */ enumerator
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| H A D | i386-reg.tbl | 102 ebx, Class=Reg|Instance=RegB|Dword|BaseIndex, 0, 3, 3, Dw2Inval
134 rbx, Class=Reg|Instance=RegB|Qword|BaseIndex, 0, 3, Dw2Inval, 3
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| H A D | ChangeLog-2019 | 484 * i386-gen.c (operand_instances): Add RegB entry.
485 * i386-opc.h (enum operand_instance): Add RegB.
486 * i386-opc.tbl (RegC, RegD, RegB): Define.
493 (ebx, rbx): Add Instance=RegB.
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| H A D | i386-gen.c | 524 INSTANCE (RegB),
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| H A D | i386-opc.tbl | 41 #define RegB Instance=RegB
3067 … CheckOperandSize|IgnoreSize|NoSuf|NoRex64, { Acc|Dword|Qword, RegC|Dword|Qword, RegB|Dword|Qword }
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 2131 for (auto &RegB : UsesB) { in isDependent() local
2133 if (RegA == RegB) in isDependent()
2138 if (RegB == *SubRegs) in isDependent()
2141 if (Register::isPhysicalRegister(RegB)) in isDependent()
2142 for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs) in isDependent()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 517 Register RegB = Root.getOperand(AddOpIdx).getReg(); in getFMAPatterns() local
518 MachineInstr *Prev = MRI->getUniqueVRegDef(RegB); in getFMAPatterns()
865 RegA21, RegB; in reassociateFMA() local
870 GetFMAInstrInfo(Root, RegM31, RegM32, RegB, KillM31, KillM32, KillB); in reassociateFMA()
1020 .addReg(RegB, getKillRegState(RegB)) in reassociateFMA()
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| /netbsd-src/external/gpl3/gdb.old/dist/opcodes/ |
| H A D | ChangeLog-2019 | 484 * i386-gen.c (operand_instances): Add RegB entry.
485 * i386-opc.h (enum operand_instance): Add RegB.
486 * i386-opc.tbl (RegC, RegD, RegB): Define.
493 (ebx, rbx): Add Instance=RegB.
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| /netbsd-src/external/gpl3/gdb/dist/opcodes/ |
| H A D | ChangeLog-2019 | 484 * i386-gen.c (operand_instances): Add RegB entry.
485 * i386-opc.h (enum operand_instance): Add RegB.
486 * i386-opc.tbl (RegC, RegD, RegB): Define.
493 (ebx, rbx): Add Instance=RegB.
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