| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsTargetStreamer.h | 122 void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
126 void emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc,
128 void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc,
130 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
132 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
134 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
136 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
138 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
140 void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,
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| H A D | MipsSEFrameLowering.cpp | 463 unsigned Reg0 = in emitPrologue() local
469 std::swap(Reg0, Reg1); in emitPrologue()
472 MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); in emitPrologue()
481 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
485 std::swap(Reg0, Reg1); in emitPrologue()
488 MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); in emitPrologue()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.cpp | 169 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, in emitR() argument
173 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
178 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, in emitRX() argument
182 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
188 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, in emitRI() argument
190 emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI); in emitRI()
193 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR() argument
195 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
208 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX() argument
213 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRX()
[all …]
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| H A D | MipsMCCodeEmitter.cpp | 98 unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0); in LowerCompactBranch() local
103 assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!"); in LowerCompactBranch()
104 if (Reg0 < Reg1) in LowerCompactBranch()
107 if (Reg0 >= Reg1) in LowerCompactBranch()
111 if (Reg1 >= Reg0) in LowerCompactBranch()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPeephole.cpp | 237 Register Reg0 = Op0.getReg(); in runOnMachineFunction() local
238 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0); in runOnMachineFunction()
242 if (Reg0.isVirtual()) { in runOnMachineFunction()
244 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) { in runOnMachineFunction()
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| H A D | HexagonBitTracker.cpp | 314 unsigned Reg0 = Reg[0].Reg; in evaluate() local
840 return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs); in evaluate()
842 return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs); in evaluate()
844 return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs); in evaluate()
846 return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs); in evaluate()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 747 uint16_t Reg0 = 0; variable
755 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; in MCRegUnitRootIterator()
761 return Reg0;
766 return Reg0; in isValid()
772 Reg0 = Reg1;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 2131 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLD() local
2153 Ops.push_back(Reg0); in SelectVLD()
2156 Ops.push_back(Reg0); in SelectVLD()
2169 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain }; in SelectVLD()
2182 Ops.push_back(Reg0); in SelectVLD()
2186 Ops.push_back(Reg0); in SelectVLD()
2266 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVST() local
2313 Ops.push_back(Reg0); in SelectVST()
2317 Ops.push_back(Reg0); in SelectVST()
2342 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain }; in SelectVST()
[all …]
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| H A D | Thumb2SizeReduction.cpp | 756 Register Reg0 = MI->getOperand(0).getReg(); in ReduceTo2Addr() local
762 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) in ReduceTo2Addr()
765 if (Reg0 != Reg2) { in ReduceTo2Addr()
768 if (Reg1 != Reg0) in ReduceTo2Addr()
775 } else if (Reg0 != Reg1) { in ReduceTo2Addr()
780 MI->getOperand(CommOpIdx2).getReg() != Reg0) in ReduceTo2Addr()
787 if (Entry.LowRegs2 && !isARMLowRegister(Reg0)) in ReduceTo2Addr()
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| H A D | ARMAsmPrinter.cpp | 322 Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); in PrintAsmOperand() local
323 O << ARMInstPrinter::getRegisterName(Reg0) << ", "; in PrintAsmOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelDAGToDAG.cpp | 224 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); in tryInlineAsm() local
247 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0, in tryInlineAsm()
262 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32, in tryInlineAsm()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 184 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register(); in commuteInstructionImpl() local
206 if (HasDef && Reg0 == Reg1 && in commuteInstructionImpl()
209 Reg0 = Reg2; in commuteInstructionImpl()
211 } else if (HasDef && Reg0 == Reg2 && in commuteInstructionImpl()
214 Reg0 = Reg1; in commuteInstructionImpl()
228 CommutedMI->getOperand(0).setReg(Reg0); in commuteInstructionImpl()
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| H A D | RegisterCoalescer.cpp | 2606 Register Reg0; in valuesIdentical() local
2607 std::tie(Orig0, Reg0) = followCopyChain(Value0); in valuesIdentical()
2608 if (Orig0 == Value1 && Reg0 == Other.Reg) in valuesIdentical()
2618 return Orig0 == Orig1 && Reg0 == Reg1; in valuesIdentical()
2624 return Orig0->def == Orig1->def && Reg0 == Reg1; in valuesIdentical()
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| H A D | RegAllocFast.cpp | 1188 Register Reg0 = MO0.getReg(); in allocateInstruction() local
1190 const TargetRegisterClass &RC0 = *MRI->getRegClass(Reg0); in allocateInstruction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMInstPrinter.cpp | 1437 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwo() local
1440 printRegName(O, Reg0); in printVectorListTwo()
1450 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpaced() local
1453 printRegName(O, Reg0); in printVectorListTwoSpaced()
1505 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoAllLanes() local
1508 printRegName(O, Reg0); in printVectorListTwoAllLanes()
1552 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpacedAllLanes() local
1555 printRegName(O, Reg0); in printVectorListTwoSpacedAllLanes()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ExpandPseudo.cpp | 467 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); in ExpandMI() local
471 .addReg(Reg0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandMI()
501 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); in ExpandMI() local
514 MIBLo.addReg(Reg0, getKillRegState(SrcIsKill)); in ExpandMI()
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| H A D | X86InstrInfo.cpp | 5632 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register(); in foldMemoryOperandImpl() local
5642 if ((HasDef && Reg0 == Reg1 && Tied1) || in foldMemoryOperandImpl()
5643 (HasDef && Reg0 == Reg2 && Tied2)) in foldMemoryOperandImpl()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 759 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
762 .addImm(Reg0) in InsertSEH()
772 Register Reg0 = MBBI->getOperand(1).getReg(); in InsertSEH() local
774 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
780 .addImm(RegInfo->getSEHRegNum(Reg0)) in InsertSEH()
810 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); in InsertSEH() local
813 .addImm(Reg0) in InsertSEH()
821 Register Reg0 = MBBI->getOperand(0).getReg(); in InsertSEH() local
823 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
829 .addImm(RegInfo->getSEHRegNum(Reg0)) in InsertSEH()
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| /netbsd-src/sys/arch/hpc/stand/hpcboot/arm/ |
| H A D | arm.asm | 192 ; Reg0 ID (R)
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.h | 749 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
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| H A D | AMDGPUBaseInfo.cpp | 1473 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) { in isRegIntersect() argument
1474 for (MCRegAliasIterator R(Reg0, TRI, true); R.isValid(); ++R) { in isRegIntersect()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 1169 Register Reg0 = MI.getOperand(0).getReg(); in commuteInstructionImpl() local
1179 if (Reg0 == Reg1) { in commuteInstructionImpl()
1199 Register Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg(); in commuteInstructionImpl() local
1202 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) in commuteInstructionImpl()
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