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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DRegister.h20 unsigned Reg; variable
23 constexpr Register(unsigned Val = 0): Reg(Val) {} in Reg() function
24 constexpr Register(MCRegister Val): Reg(Val) {} in Register()
36 static_assert(std::numeric_limits<decltype(Reg)>::max() >= 0xFFFFFFFF,
44 static bool isStackSlot(unsigned Reg) { in isStackSlot() argument
45 return MCRegister::isStackSlot(Reg); in isStackSlot()
49 bool isStack() const { return MCRegister::isStackSlot(Reg); } in isStack()
52 static int stackSlot2Index(Register Reg) { in stackSlot2Index() argument
53 assert(Reg.isStack() && "Not a stack slot"); in stackSlot2Index()
54 return int(Reg - MCRegister::FirstStackSlot); in stackSlot2Index()
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H A DMachineRegisterInfo.h60 virtual void MRI_NoteNewVirtualRegister(Register Reg) = 0;
125 return MO->Contents.Reg.Next; in getNextOperandForReg()
235 void disableCalleeSavedRegister(MCRegister Reg);
256 void verifyUseList(Register Reg) const;
286 inline iterator_range<reg_iterator> reg_operands(Register Reg) const { in reg_operands() argument
287 return make_range(reg_begin(Reg), reg_end()); in reg_operands()
302 reg_instructions(Register Reg) const { in reg_instructions() argument
303 return make_range(reg_instr_begin(Reg), reg_instr_end()); in reg_instructions()
317 inline iterator_range<reg_bundle_iterator> reg_bundles(Register Reg) const { in reg_bundles() argument
318 return make_range(reg_bundle_begin(Reg), reg_bundle_end()); in reg_bundles()
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H A DLiveVariables.h108 bool isLiveIn(const MachineBasicBlock &MBB, Register Reg,
151 bool HandlePhysRegKill(Register Reg, MachineInstr *MI);
156 void HandlePhysRegUse(Register Reg, MachineInstr &MI);
157 void HandlePhysRegDef(Register Reg, MachineInstr *MI,
163 MachineInstr *FindLastRefOrPartRef(Register Reg);
168 MachineInstr *FindLastPartialDef(Register Reg,
186 bool RegisterDefIsDead(MachineInstr &MI, Register Reg) const;
193 void replaceKillInstruction(Register Reg, MachineInstr &OldMI,
210 bool removeVirtualRegisterKilled(Register Reg, MachineInstr &MI) { in removeVirtualRegisterKilled() argument
211 if (!getVarInfo(Reg).removeKill(MI)) in removeVirtualRegisterKilled()
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H A DLiveIntervals.h114 LiveInterval &getInterval(Register Reg) { in getInterval() argument
115 if (hasInterval(Reg)) in getInterval()
116 return *VirtRegIntervals[Reg.id()]; in getInterval()
118 return createAndComputeVirtRegInterval(Reg); in getInterval()
121 const LiveInterval &getInterval(Register Reg) const { in getInterval() argument
122 return const_cast<LiveIntervals*>(this)->getInterval(Reg); in getInterval()
125 bool hasInterval(Register Reg) const { in hasInterval() argument
126 return VirtRegIntervals.inBounds(Reg.id()) && in hasInterval()
127 VirtRegIntervals[Reg.id()]; in hasInterval()
131 LiveInterval &createEmptyInterval(Register Reg) { in createEmptyInterval() argument
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp58 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) { in setRegClass() argument
60 VRegInfo[Reg].first = RC; in setRegClass()
63 void MachineRegisterInfo::setRegBank(Register Reg, in setRegBank() argument
65 VRegInfo[Reg].first = &RegBank; in setRegBank()
69 constrainRegClass(MachineRegisterInfo &MRI, Register Reg, in constrainRegClass() argument
80 MRI.setRegClass(Reg, NewRC); in constrainRegClass()
85 MachineRegisterInfo::constrainRegClass(Register Reg, in constrainRegClass() argument
88 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs); in constrainRegClass()
92 MachineRegisterInfo::constrainRegAttrs(Register Reg, in constrainRegAttrs() argument
95 const LLT RegTy = getType(Reg); in constrainRegAttrs()
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H A DAggressiveAntiDepBreaker.cpp70 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { in GetGroup() argument
71 unsigned Node = GroupNodeIndices[Reg]; in GetGroup()
83 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) { in GetGroupRegs() local
84 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0)) in GetGroupRegs()
85 Regs.push_back(Reg); in GetGroupRegs()
104 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) { in LeaveGroup() argument
110 GroupNodeIndices[Reg] = idx; in LeaveGroup()
114 bool AggressiveAntiDepState::IsLive(unsigned Reg) { in IsLive() argument
117 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u)); in IsLive()
159 unsigned Reg = *AI; in StartBlock() local
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H A DLiveVariables.cpp84 LiveVariables::VarInfo &LiveVariables::getVarInfo(Register Reg) { in getVarInfo() argument
85 assert(Reg.isVirtual() && "getVarInfo: not a virtual register!"); in getVarInfo()
86 VirtRegInfo.grow(Reg); in getVarInfo()
87 return VirtRegInfo[Reg]; in getVarInfo()
128 void LiveVariables::HandleVirtRegUse(Register Reg, MachineBasicBlock *MBB, in HandleVirtRegUse() argument
130 assert(MRI->getVRegDef(Reg) && "Register use before def!"); in HandleVirtRegUse()
134 VarInfo &VRInfo = getVarInfo(Reg); in HandleVirtRegUse()
165 if (MBB == MRI->getVRegDef(Reg)->getParent()) in HandleVirtRegUse()
176 MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(Reg)->getParent(), Pred); in HandleVirtRegUse()
179 void LiveVariables::HandleVirtRegDef(Register Reg, MachineInstr &MI) { in HandleVirtRegDef() argument
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H A DFixupStatepointCallerSaved.cpp96 static unsigned getRegisterSize(const TargetRegisterInfo &TRI, Register Reg) { in getRegisterSize() argument
97 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg); in getRegisterSize()
114 static Register performCopyPropagation(Register Reg, in performCopyPropagation() argument
119 int Idx = RI->findRegisterUseOperandIdx(Reg, false, &TRI); in performCopyPropagation()
122 return Reg; in performCopyPropagation()
126 return Reg; in performCopyPropagation()
132 if (It->readsRegister(Reg, &TRI) && !Use) in performCopyPropagation()
134 if (It->modifiesRegister(Reg, &TRI)) { in performCopyPropagation()
141 return Reg; in performCopyPropagation()
144 if (!DestSrc || DestSrc->Destination->getReg() != Reg) in performCopyPropagation()
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H A DCriticalAntiDepBreaker.cpp71 unsigned Reg = *AI; in StartBlock() local
72 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
73 KillIndices[Reg] = BBSize; in StartBlock()
74 DefIndices[Reg] = ~0u; in StartBlock()
85 unsigned Reg = *I; in StartBlock() local
86 if (!IsReturnBlock && !Pristine.test(Reg)) in StartBlock()
89 unsigned Reg = *AI; in StartBlock() local
90 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
91 KillIndices[Reg] = BBSize; in StartBlock()
92 DefIndices[Reg] = ~0u; in StartBlock()
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H A DRegisterScavenging.cpp53 void RegScavenger::setRegUsed(Register Reg, LaneBitmask LaneMask) { in setRegUsed() argument
54 LiveUnits.addRegMasked(Reg, LaneMask); in setRegUsed()
77 SI.Reg = 0; in init()
100 void RegScavenger::addRegUnits(BitVector &BV, MCRegister Reg) { in addRegUnits() argument
101 for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) in addRegUnits()
105 void RegScavenger::removeRegUnits(BitVector &BV, MCRegister Reg) { in removeRegUnits() argument
106 for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) in removeRegUnits()
139 MCRegister Reg = MO.getReg().asMCReg(); in determineKillsAndDefs() local
146 addRegUnits(KillRegUnits, Reg); in determineKillsAndDefs()
150 addRegUnits(KillRegUnits, Reg); in determineKillsAndDefs()
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H A DLivePhysRegs.cpp85 Register Reg = O->getReg(); in stepForward() local
86 if (!Register::isPhysicalRegister(Reg)) in stepForward()
91 Clobbers.push_back(std::make_pair(Reg, &*O)); in stepForward()
96 removeReg(Reg); in stepForward()
103 for (auto Reg : Clobbers) { in stepForward() local
106 if (Reg.second->isReg() && Reg.second->isDead()) in stepForward()
108 if (Reg.second->isRegMask() && in stepForward()
109 MachineOperand::clobbersPhysReg(Reg.second->getRegMask(), Reg.first)) in stepForward()
111 addReg(Reg.first); in stepForward()
140 MCPhysReg Reg) const { in available()
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H A DMachineInstrBundle.cpp156 Register Reg = MO.getReg(); in finalizeBundle() local
157 if (!Reg) in finalizeBundle()
160 if (LocalDefSet.count(Reg)) { in finalizeBundle()
164 KilledDefSet.insert(Reg); in finalizeBundle()
166 if (ExternUseSet.insert(Reg).second) { in finalizeBundle()
167 ExternUses.push_back(Reg); in finalizeBundle()
169 UndefUseSet.insert(Reg); in finalizeBundle()
173 KilledUseSet.insert(Reg); in finalizeBundle()
179 Register Reg = MO.getReg(); in finalizeBundle() local
180 if (!Reg) in finalizeBundle()
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H A DRDFRegisters.cpp49 if (UnitInfos[U].Reg != 0) in PhysicalRegisterInfo()
57 UnitInfos[U].Reg = F; in PhysicalRegisterInfo()
62 UI.Reg = F; in PhysicalRegisterInfo()
106 std::set<RegisterId> PhysicalRegisterInfo::getAliasSet(RegisterId Reg) const { in getAliasSet()
109 assert(isRegMaskId(Reg) || Register::isPhysicalRegister(Reg)); in getAliasSet()
110 if (isRegMaskId(Reg)) { in getAliasSet()
112 const uint32_t *MB = getRegMaskBits(Reg); in getAliasSet()
120 if (MI != Reg && aliasMM(RegisterRef(Reg), RegisterRef(MI))) in getAliasSet()
126 for (MCRegAliasIterator AI(Reg, &TRI, false); AI.isValid(); ++AI) in getAliasSet()
130 if (aliasRM(RegisterRef(Reg), RegisterRef(MI))) in getAliasSet()
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H A DCalcSpillWeights.cpp38 unsigned Reg = Register::index2VirtReg(I); in calculateSpillWeightsAndHints() local
39 if (MRI.reg_nodbg_empty(Reg)) in calculateSpillWeightsAndHints()
41 calculateSpillWeightAndHint(LIS.getInterval(Reg)); in calculateSpillWeightsAndHints()
46 static Register copyHint(const MachineInstr *MI, unsigned Reg, in copyHint() argument
51 if (MI->getOperand(0).getReg() == Reg) { in copyHint()
67 const TargetRegisterClass *rc = MRI.getRegClass(Reg); in copyHint()
83 unsigned Reg = LI.reg(); in isRematerializable() local
84 unsigned Original = VRM.getOriginal(Reg); in isRematerializable()
101 if (MI->getOperand(0).getReg() != Reg) in isRematerializable()
105 Reg = MI->getOperand(1).getReg(); in isRematerializable()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonVectorPrint.cpp73 static bool isVecReg(unsigned Reg) { in isVecReg() argument
74 return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) || in isVecReg()
75 (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) || in isVecReg()
76 (Reg >= Hexagon::WR0 && Reg <= Hexagon::WR15) || in isVecReg()
77 (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3); in isVecReg()
96 static void addAsmInstr(MachineBasicBlock *MBB, unsigned Reg, in addAsmInstr() argument
100 std::string VDescStr = ".long 0x1dffe0" + getStringReg(Reg); in addAsmInstr()
108 static bool getInstrVecReg(const MachineInstr &MI, unsigned &Reg) { in getInstrVecReg() argument
112 Reg = MI.getOperand(0).getReg(); in getInstrVecReg()
113 if (isVecReg(Reg)) in getInstrVecReg()
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/netbsd-src/external/gpl3/binutils/dist/opcodes/
H A Di386-reg.tbl25 al, Class=Reg|Instance=Accum|Byte, 0, 0, Dw2Inval, Dw2Inval
26 cl, Class=Reg|Instance=RegC|Byte, 0, 1, Dw2Inval, Dw2Inval
27 dl, Class=Reg|Byte, 0, 2, Dw2Inval, Dw2Inval
28 bl, Class=Reg|Byte, 0, 3, Dw2Inval, Dw2Inval
29 ah, Class=Reg|Byte, 0, 4, Dw2Inval, Dw2Inval
30 ch, Class=Reg|Byte, 0, 5, Dw2Inval, Dw2Inval
31 dh, Class=Reg|Byte, 0, 6, Dw2Inval, Dw2Inval
32 bh, Class=Reg|Byte, 0, 7, Dw2Inval, Dw2Inval
33 axl, Class=Reg|Byte, RegRex64, 0, Dw2Inval, Dw2Inval
34 cxl, Class=Reg|Byte, RegRex64, 1, Dw2Inval, Dw2Inval
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/
H A DMCRegister.h24 unsigned Reg; variable
27 constexpr MCRegister(unsigned Val = 0): Reg(Val) {} in Reg() function
39 static_assert(std::numeric_limits<decltype(Reg)>::max() >= 0xFFFFFFFF,
50 static bool isStackSlot(unsigned Reg) { in isStackSlot() argument
51 return FirstStackSlot <= Reg && Reg < VirtualRegFlag; in isStackSlot()
56 static bool isPhysicalRegister(unsigned Reg) { in isPhysicalRegister() argument
57 return FirstPhysicalReg <= Reg && Reg < FirstStackSlot; in isPhysicalRegister()
61 return Reg;
71 return Reg; in id()
74 bool isValid() const { return Reg != NoRegister; } in isValid()
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H A DMCRegisterInfo.h68 bool contains(MCRegister Reg) const { in contains() argument
69 unsigned RegNo = unsigned(Reg); in contains()
252 mc_difflist_iterator(MCRegister Reg, const MCPhysReg *DiffList) { in mc_difflist_iterator() argument
253 Iter.init(Reg, DiffList); in mc_difflist_iterator()
290 mc_subreg_iterator(MCRegister Reg, const MCRegisterInfo *MCRI) in mc_subreg_iterator() argument
291 : mc_difflist_iterator(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs) {} in mc_subreg_iterator()
302 mc_superreg_iterator(MCRegister Reg, const MCRegisterInfo *MCRI) in mc_superreg_iterator() argument
303 : mc_difflist_iterator(Reg, in mc_superreg_iterator()
304 MCRI->DiffLists + MCRI->get(Reg).SuperRegs) {} in mc_superreg_iterator()
309 iterator_range<mc_subreg_iterator> subregs(MCRegister Reg) const { in subregs() argument
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/netbsd-src/sys/external/bsd/acpica/dist/hardware/
H A Dhwregs.c60 ACPI_GENERIC_ADDRESS *Reg,
95 ACPI_GENERIC_ADDRESS *Reg, in AcpiHwGetAccessBitWidth() argument
115 if (!Reg->BitOffset && Reg->BitWidth && in AcpiHwGetAccessBitWidth()
116 ACPI_IS_POWER_OF_TWO (Reg->BitWidth) && in AcpiHwGetAccessBitWidth()
117 ACPI_IS_ALIGNED (Reg->BitWidth, 8)) in AcpiHwGetAccessBitWidth()
119 AccessBitWidth = Reg->BitWidth; in AcpiHwGetAccessBitWidth()
121 else if (Reg->AccessWidth) in AcpiHwGetAccessBitWidth()
123 AccessBitWidth = ACPI_ACCESS_BIT_WIDTH (Reg->AccessWidth); in AcpiHwGetAccessBitWidth()
128 Reg->BitOffset + Reg->BitWidth); in AcpiHwGetAccessBitWidth()
144 if (Reg->SpaceId == ACPI_ADR_SPACE_SYSTEM_IO) in AcpiHwGetAccessBitWidth()
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/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/PowerPC/
H A DTarget.cpp32 std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
38 void fillMemoryOperands(InstructionTemplate &IT, unsigned Reg,
54 static MCInst loadImmediate(unsigned Reg, unsigned RegBitWidth, in loadImmediate() argument
62 .addReg(Reg) in loadImmediate()
74 unsigned Reg, in fillMemoryOperands() argument
88 setMemOp(IT, MemOpIdx + 2, MCOperand::createReg(Reg)); // BaseReg in fillMemoryOperands()
92 unsigned Reg, in setRegTo() argument
98 if (PPC::GPRCRegClass.contains(Reg)) in setRegTo()
99 return {loadImmediate(Reg, 32, Value)}; in setRegTo()
100 if (PPC::G8RCRegClass.contains(Reg)) in setRegTo()
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/netbsd-src/external/gpl3/binutils.old/dist/opcodes/
H A Di386-reg.tbl22 al, Class=Reg|Instance=Accum|Byte, 0, 0, Dw2Inval, Dw2Inval
23 cl, Class=Reg|Instance=RegC|Byte, 0, 1, Dw2Inval, Dw2Inval
24 dl, Class=Reg|Byte, 0, 2, Dw2Inval, Dw2Inval
25 bl, Class=Reg|Byte, 0, 3, Dw2Inval, Dw2Inval
26 ah, Class=Reg|Byte, 0, 4, Dw2Inval, Dw2Inval
27 ch, Class=Reg|Byte, 0, 5, Dw2Inval, Dw2Inval
28 dh, Class=Reg|Byte, 0, 6, Dw2Inval, Dw2Inval
29 bh, Class=Reg|Byte, 0, 7, Dw2Inval, Dw2Inval
30 axl, Class=Reg|Byte, RegRex64, 0, Dw2Inval, Dw2Inval
31 cxl, Class=Reg|Byte, RegRex64, 1, Dw2Inval, Dw2Inval
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64TargetStreamer.h49 virtual void EmitARM64WinCFISaveReg(unsigned Reg, int Offset) {} in EmitARM64WinCFISaveReg() argument
50 virtual void EmitARM64WinCFISaveRegX(unsigned Reg, int Offset) {} in EmitARM64WinCFISaveRegX() argument
51 virtual void EmitARM64WinCFISaveRegP(unsigned Reg, int Offset) {} in EmitARM64WinCFISaveRegP() argument
52 virtual void EmitARM64WinCFISaveRegPX(unsigned Reg, int Offset) {} in EmitARM64WinCFISaveRegPX() argument
53 virtual void EmitARM64WinCFISaveLRPair(unsigned Reg, int Offset) {} in EmitARM64WinCFISaveLRPair() argument
54 virtual void EmitARM64WinCFISaveFReg(unsigned Reg, int Offset) {} in EmitARM64WinCFISaveFReg() argument
55 virtual void EmitARM64WinCFISaveFRegX(unsigned Reg, int Offset) {} in EmitARM64WinCFISaveFRegX() argument
56 virtual void EmitARM64WinCFISaveFRegP(unsigned Reg, int Offset) {} in EmitARM64WinCFISaveFRegP() argument
57 virtual void EmitARM64WinCFISaveFRegPX(unsigned Reg, int Offset) {} in EmitARM64WinCFISaveFRegPX() argument
102 void EmitARM64WinCFISaveReg(unsigned Reg, int Offset) override;
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H A DAArch64InstPrinter.cpp746 unsigned Reg = MI->getOperand(OpNum++).getReg(); in printInst() local
747 if (Reg != AArch64::XZR) in printInst()
748 O << ", " << getRegisterName(Reg); in printInst()
880 unsigned Reg = Op.getReg(); in printOperand() local
881 O << getRegisterName(Reg); in printOperand()
921 unsigned Reg = Op.getReg(); in printPostIncOperand() local
922 if (Reg == AArch64::XZR) in printPostIncOperand()
925 O << getRegisterName(Reg); in printPostIncOperand()
935 unsigned Reg = Op.getReg(); in printVRegOperand() local
936 O << getRegisterName(Reg, AArch64::vreg); in printVRegOperand()
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H A DAArch64WinCOFFStreamer.cpp69 int Reg, in EmitARM64WinUnwindCode() argument
76 auto Inst = WinEH::Instruction(UnwindCode, Label, Reg, Offset); in EmitARM64WinUnwindCode()
104 void AArch64TargetWinCOFFStreamer::EmitARM64WinCFISaveReg(unsigned Reg, in EmitARM64WinCFISaveReg() argument
108 EmitARM64WinUnwindCode(Win64EH::UOP_SaveReg, Reg, Offset); in EmitARM64WinCFISaveReg()
111 void AArch64TargetWinCOFFStreamer::EmitARM64WinCFISaveRegX(unsigned Reg, in EmitARM64WinCFISaveRegX() argument
113 EmitARM64WinUnwindCode(Win64EH::UOP_SaveRegX, Reg, Offset); in EmitARM64WinCFISaveRegX()
116 void AArch64TargetWinCOFFStreamer::EmitARM64WinCFISaveRegP(unsigned Reg, in EmitARM64WinCFISaveRegP() argument
118 EmitARM64WinUnwindCode(Win64EH::UOP_SaveRegP, Reg, Offset); in EmitARM64WinCFISaveRegP()
121 void AArch64TargetWinCOFFStreamer::EmitARM64WinCFISaveRegPX(unsigned Reg, in EmitARM64WinCFISaveRegPX() argument
123 EmitARM64WinUnwindCode(Win64EH::UOP_SaveRegPX, Reg, Offset); in EmitARM64WinCFISaveRegPX()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp65 bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const;
89 Register Reg = MI->getOperand(1).getReg(); in getAccDefMI() local
90 if (Register::isPhysicalRegister(Reg)) in getAccDefMI()
94 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
99 Reg = DefMI->getOperand(1).getReg(); in getAccDefMI()
100 if (Register::isVirtualRegister(Reg)) { in getAccDefMI()
101 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
105 Reg = DefMI->getOperand(2).getReg(); in getAccDefMI()
106 if (Register::isVirtualRegister(Reg)) { in getAccDefMI()
107 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
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