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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVSchedRocket.td177 def : ReadAdvance<ReadJmp, 0>;
178 def : ReadAdvance<ReadJalr, 0>;
179 def : ReadAdvance<ReadCSR, 0>;
180 def : ReadAdvance<ReadStoreData, 0>;
181 def : ReadAdvance<ReadMemBase, 0>;
182 def : ReadAdvance<ReadIALU, 0>;
183 def : ReadAdvance<ReadIALU32, 0>;
184 def : ReadAdvance<ReadShiftImm, 0>;
185 def : ReadAdvance<ReadShiftImm32, 0>;
186 def : ReadAdvance<ReadShiftReg, 0>;
[all …]
H A DRISCVSchedSiFive7.td165 def : ReadAdvance<ReadJmp, 0>;
166 def : ReadAdvance<ReadJalr, 0>;
167 def : ReadAdvance<ReadCSR, 0>;
168 def : ReadAdvance<ReadStoreData, 0>;
169 def : ReadAdvance<ReadMemBase, 0>;
170 def : ReadAdvance<ReadIALU, 0>;
171 def : ReadAdvance<ReadIALU32, 0>;
172 def : ReadAdvance<ReadShiftImm, 0>;
173 def : ReadAdvance<ReadShiftImm32, 0>;
174 def : ReadAdvance<ReadShiftReg, 0>;
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H A DRISCVScheduleB.td56 def : ReadAdvance<ReadSHXADD, 0>;
57 def : ReadAdvance<ReadSHXADD32, 0>;
76 def : ReadAdvance<ReadRotateImm, 0>;
77 def : ReadAdvance<ReadRotateImm32, 0>;
78 def : ReadAdvance<ReadRotateReg, 0>;
79 def : ReadAdvance<ReadRotateReg32, 0>;
80 def : ReadAdvance<ReadCLZ, 0>;
81 def : ReadAdvance<ReadCLZ32, 0>;
82 def : ReadAdvance<ReadCTZ, 0>;
83 def : ReadAdvance<ReadCTZ32, 0>;
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H A DRISCVSchedule.td209 def : ReadAdvance<ReadFALU16, 0>;
210 def : ReadAdvance<ReadFClass16, 0>;
211 def : ReadAdvance<ReadFCvtF16ToF64, 0>;
212 def : ReadAdvance<ReadFCvtF64ToF16, 0>;
213 def : ReadAdvance<ReadFCvtI64ToF16, 0>;
214 def : ReadAdvance<ReadFCvtF32ToF16, 0>;
215 def : ReadAdvance<ReadFCvtI32ToF16, 0>;
216 def : ReadAdvance<ReadFCvtF16ToI64, 0>;
217 def : ReadAdvance<ReadFCvtF16ToF32, 0>;
218 def : ReadAdvance<ReadFCvtF16ToI32, 0>;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkor.td103 // These ReadAdvance entries are not used in the Falkor sched model.
104 def : ReadAdvance<ReadI, 0>;
105 def : ReadAdvance<ReadISReg, 0>;
106 def : ReadAdvance<ReadIEReg, 0>;
107 def : ReadAdvance<ReadIM, 0>;
108 def : ReadAdvance<ReadIMA, 0>;
109 def : ReadAdvance<ReadID, 0>;
110 def : ReadAdvance<ReadExtrHi, 0>;
111 def : ReadAdvance<ReadAdrBase, 0>;
112 def : ReadAdvance<ReadVLD, 0>;
H A DAArch64SchedKryo.td110 def : ReadAdvance<ReadI, 0>;
111 def : ReadAdvance<ReadISReg, 0>;
112 def : ReadAdvance<ReadIEReg, 0>;
113 def : ReadAdvance<ReadIM, 0>;
114 def : ReadAdvance<ReadIMA, 0>;
115 def : ReadAdvance<ReadID, 0>;
116 def : ReadAdvance<ReadExtrHi, 0>;
117 def : ReadAdvance<ReadAdrBase, 0>;
118 def : ReadAdvance<ReadVLD, 0>;
H A DAArch64SchedThunderX.td191 def : ReadAdvance<ReadExtrHi, 1>;
192 def : ReadAdvance<ReadAdrBase, 2>;
193 def : ReadAdvance<ReadVLD, 2>;
199 // ReadAdvance applies to Extended registers as well, even though there is
201 def : ReadAdvance<ReadI, 2, [WriteImm, WriteI,
225 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
229 def : ReadAdvance<ReadIMA, 2, [WriteImm, WriteI,
235 def : ReadAdvance<ReadID, 1, [WriteImm, WriteI,
H A DAArch64SchedA53.td149 def : ReadAdvance<ReadExtrHi, 0>;
150 def : ReadAdvance<ReadAdrBase, 0>;
151 def : ReadAdvance<ReadVLD, 0>;
156 // ReadAdvance applies to Extended registers as well, even though there is
158 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
182 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
186 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
192 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
H A DAArch64SchedA55.td175 def : ReadAdvance<ReadVLD, 0>;
176 def : ReadAdvance<ReadExtrHi, 1>;
177 def : ReadAdvance<ReadAdrBase, 1>;
183 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
207 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
211 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
217 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
H A DAArch64SchedTSV110.td107 def : ReadAdvance<ReadI, 0>;
108 def : ReadAdvance<ReadISReg, 0>;
109 def : ReadAdvance<ReadIEReg, 0>;
110 def : ReadAdvance<ReadIM, 0>;
111 def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>;
112 def : ReadAdvance<ReadID, 0>;
113 def : ReadAdvance<ReadExtrHi, 0>;
114 def : ReadAdvance<ReadAdrBase, 0>;
115 def : ReadAdvance<ReadVLD, 0>;
H A DAArch64SchedExynosM3.td269 def : ReadAdvance<ReadI, 0>;
270 def : ReadAdvance<ReadISReg, 0>;
271 def : ReadAdvance<ReadIEReg, 0>;
272 def : ReadAdvance<ReadIM, 0>;
274 def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>;
275 def : ReadAdvance<ReadID, 0>;
276 def : ReadAdvance<ReadExtrHi, 0>;
277 def : ReadAdvance<ReadAdrBase, 0>;
278 def : ReadAdvance<ReadVLD, 0>;
H A DAArch64SchedCyclone.td185 def : ReadAdvance<ReadExtrHi, 1>;
634 def : ReadAdvance<ReadVLD, 5>;
864 def : ReadAdvance<ReadI, 0>;
865 def : ReadAdvance<ReadISReg, 0>;
866 def : ReadAdvance<ReadIEReg, 0>;
867 def : ReadAdvance<ReadIM, 0>;
868 def : ReadAdvance<ReadIMA, 0>;
869 def : ReadAdvance<ReadID, 0>;
H A DAArch64SchedA57.td111 def : ReadAdvance<ReadI, 0>;
112 def : ReadAdvance<ReadISReg, 0>;
113 def : ReadAdvance<ReadIEReg, 0>;
114 def : ReadAdvance<ReadIM, 0>;
115 def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>;
116 def : ReadAdvance<ReadID, 0>;
117 def : ReadAdvance<ReadExtrHi, 0>;
118 def : ReadAdvance<ReadAdrBase, 0>;
119 def : ReadAdvance<ReadVLD, 0>;
H A DAArch64SchedExynosM5.td608 def : ReadAdvance<ReadI, 0>;
609 def : ReadAdvance<ReadISReg, 0>;
610 def : ReadAdvance<ReadIEReg, 0>;
611 def : ReadAdvance<ReadIM, 0>;
613 def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>;
614 def : ReadAdvance<ReadID, 0>;
615 def : ReadAdvance<ReadExtrHi, 0>;
616 def : ReadAdvance<ReadAdrBase, 0>;
617 def : ReadAdvance<ReadVLD, 0>;
H A DAArch64SchedExynosM4.td573 def : ReadAdvance<ReadI, 0>;
574 def : ReadAdvance<ReadISReg, 0>;
575 def : ReadAdvance<ReadIEReg, 0>;
576 def : ReadAdvance<ReadIM, 0>;
578 def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>;
579 def : ReadAdvance<ReadID, 0>;
580 def : ReadAdvance<ReadExtrHi, 0>;
581 def : ReadAdvance<ReadAdrBase, 0>;
582 def : ReadAdvance<ReadVLD, 0>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp496 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID); in collectWrites() local
497 if (ReadAdvance < 0) { in collectWrites()
499 if (Elapsed < static_cast<unsigned>(-ReadAdvance)) in collectWrites()
511 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID); in collectWrites() local
512 if (ReadAdvance < 0) { in collectWrites()
514 if (Elapsed < static_cast<unsigned>(-ReadAdvance)) in collectWrites()
564 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID); in addRegisterRead() local
565 WS.addUser(WR.getSourceIndex(), &RS, ReadAdvance); in addRegisterRead()
572 unsigned ReadAdvance = static_cast<unsigned>( in addRegisterRead() local
575 assert(Elapsed < ReadAdvance && "Should not have been added to the set!"); in addRegisterRead()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMScheduleM4.td100 def : ReadAdvance<ReadALU, 0>;
101 def : ReadAdvance<ReadALUsr, 0>;
102 def : ReadAdvance<ReadMUL, 0>;
103 def : ReadAdvance<ReadMAC, 0>;
134 def : ReadAdvance<ReadFPMUL, 0>;
135 def : ReadAdvance<ReadFPMAC, 0>;
H A DARMScheduleM7.td36 // ReadAdvance<0> (the default) for their source operands and Latency = 1.
175 def : ReadAdvance<ReadALUsr, 0>;
176 def : ReadAdvance<ReadMUL, 0>;
177 def : ReadAdvance<ReadMAC, 1>;
178 def : ReadAdvance<ReadALU, 0>;
179 def : ReadAdvance<ReadFPMUL, 0>;
180 def : ReadAdvance<ReadFPMAC, 3>;
H A DARMScheduleR52.td87 def : ReadAdvance<ReadALU, 1>; // Operand needed in EX1 stage
88 def : ReadAdvance<ReadALUsr, 0>; // Shift operands needed in ISS
89 def : ReadAdvance<ReadMUL, 0>;
90 def : ReadAdvance<ReadMAC, 0>;
127 def : ReadAdvance<ReadFPMUL, 1>; // mul operand read in F1
128 def : ReadAdvance<ReadFPMAC, 1>; // fp-mac operand read in F1
134 def : ReadAdvance<R52Read_ISS, 0>;
135 def : ReadAdvance<R52Read_EX1, 1>;
136 def : ReadAdvance<R52Read_EX2, 2>;
137 def : ReadAdvance<R52Read_F0, 0>;
[all …]
H A DARMScheduleA57.td266 def : ReadAdvance<ReadMUL, 0>;
763 def : ReadAdvance<ReadFPMUL, 0>;
776 // def : ReadAdvance<A57ReadVFMA, 5, [A57WriteVFMA]>;
777 // def : ReadAdvance<A57ReadVFMA, 4, [A57WriteVMUL]>;
1034 // (4 or 3 ReadAdvance)
1047 // (4 or 3 ReadAdvance)
1060 // (4 or 3 ReadAdvance)
1073 // (3 or 2 ReadAdvance)
1098 // 4cyc F1, 1cyc for accumulate sequence (3cyc ReadAdvance)
1104 // 4cyc F1, 1cyc for accumulate sequence (3cyc ReadAdvance)
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/Stages/
H A DInOrderIssueStage.cpp108 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID); in checkRegisterHazard() local
109 LLVM_DEBUG(dbgs() << "[E] ReadAdvance for #" << IR << ": " << ReadAdvance in checkRegisterHazard()
118 int CyclesLeft = WS->getCyclesLeft() - ReadAdvance; in checkRegisterHazard()
132 unsigned ReadAdvance = static_cast<unsigned>( in checkRegisterHazard() local
135 assert(Elapsed < ReadAdvance && "Should not have been added to the set!"); in checkRegisterHazard()
136 unsigned CyclesLeft = (ReadAdvance - Elapsed); in checkRegisterHazard()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/
H A DInstruction.cpp72 void WriteState::addUser(unsigned IID, ReadState *User, int ReadAdvance) { in addUser() argument
77 unsigned ReadCycles = std::max(0, CyclesLeft - ReadAdvance); in addUser()
82 Users.emplace_back(User, ReadAdvance); in addUser()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ScheduleSLM.td50 def : ReadAdvance<ReadAfterLd, 3>;
51 def : ReadAdvance<ReadAfterVecLd, 3>;
52 def : ReadAdvance<ReadAfterVecXLd, 3>;
53 def : ReadAdvance<ReadAfterVecYLd, 3>;
55 def : ReadAdvance<ReadInt2Fpu, 0>;
H A DX86ScheduleAtom.td45 def : ReadAdvance<ReadAfterLd, 3>;
46 def : ReadAdvance<ReadAfterVecLd, 3>;
47 def : ReadAdvance<ReadAfterVecXLd, 3>;
48 def : ReadAdvance<ReadAfterVecYLd, 3>;
50 def : ReadAdvance<ReadInt2Fpu, 0>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSISchedule.td163 def : ReadAdvance<MIVGPRRead, -2>;
171 def : ReadAdvance<MIMFMARead, -4>;

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