| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 205 unsigned RHSReg, bool SetFlags = false,
211 unsigned RHSReg, AArch64_AM::ShiftExtendType ShiftType,
215 unsigned RHSReg, AArch64_AM::ShiftExtendType ExtType,
240 unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
242 unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
250 unsigned RHSReg, uint64_t ShiftImm);
1210 unsigned RHSReg = getRegForValue(SI->getOperand(0)); in emitAddSub() local
1211 if (!RHSReg) in emitAddSub()
1213 return emitAddSub_rx(UseAdd, RetVT, LHSReg, RHSReg, ExtendType, in emitAddSub()
1216 unsigned RHSReg = getRegForValue(RHS); in emitAddSub() local
[all …]
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| /netbsd-src/external/gpl3/gdb.old/dist/sim/arm/ |
| H A D | armemu.h | 317 #define RHSReg (BITS ( 0, 3)) macro
343 #define DPRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \
345 #define DPSRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \
348 #define DPRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
350 #define DPSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
358 #define LSRegRHS ((BITS (4, 11) == 0) ? state->Reg[RHSReg] \
361 #define LSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
370 #define SWAPSRC (state->Reg[RHSReg])
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 54 ARMCC::CondCodes Cond, unsigned LHSReg, unsigned RHSReg,
502 unsigned LHSReg, unsigned RHSReg, in validOpRegPair() argument
505 return MRI.getType(LHSReg) == MRI.getType(RHSReg) && in validOpRegPair()
507 validReg(MRI, RHSReg, ExpectedSize, ExpectedRegBankID); in validOpRegPair()
544 auto RHSReg = MIB.getReg(3); in selectCmp() local
545 if (!validOpRegPair(MRI, LHSReg, RHSReg, Helper.OperandSize, in selectCmp()
555 if (!insertComparison(Helper, I, ResReg, ARMConds.first, LHSReg, RHSReg, in selectCmp()
562 RHSReg, ZeroReg)) in selectCmp()
564 if (!insertComparison(Helper, I, ResReg, ARMConds.second, LHSReg, RHSReg, in selectCmp()
576 unsigned LHSReg, unsigned RHSReg, in insertComparison() argument
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 2141 Register RHSReg = getRegForValue(RHS); in X86FastEmitCMoveSelect() local
2143 if (!LHSReg || !RHSReg) in X86FastEmitCMoveSelect()
2148 Register ResultReg = fastEmitInst_rri(Opc, RC, RHSReg, LHSReg, CC); in X86FastEmitCMoveSelect()
2197 Register RHSReg = getRegForValue(RHS); in X86FastEmitSSESelect() local
2200 if (!LHSReg || !RHSReg || !CmpLHSReg || !CmpRHSReg) in X86FastEmitSSESelect()
2226 unsigned MovReg = fastEmitInst_rrrr(MovOpcode, VR128X, RHSReg, CmpReg, in X86FastEmitSSESelect()
2248 Register VBlendReg = fastEmitInst_rrr(BlendOpcode, VR128, RHSReg, LHSReg, in X86FastEmitSSESelect()
2270 Register AndNReg = fastEmitInst_rr(Opc[2], VR128, CmpReg, RHSReg); in X86FastEmitSSESelect()
2340 Register RHSReg = getRegForValue(RHS); in X86FastEmitPseudoSelect() local
2341 if (!LHSReg || !RHSReg) in X86FastEmitPseudoSelect()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 320 unsigned RHSReg; in emitLogicalOp() local
322 RHSReg = materializeInt(C, MVT::i32); in emitLogicalOp()
324 RHSReg = getRegForValue(RHS); in emitLogicalOp()
325 if (!RHSReg) in emitLogicalOp()
332 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg); in emitLogicalOp()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 2878 Register RHSReg = MI.getOperand(2).getReg(); in matchHoistLogicOpWithSameOpcodeHands() local
2881 if (!MRI.hasOneNonDBGUse(LHSReg) || !MRI.hasOneNonDBGUse(RHSReg)) in matchHoistLogicOpWithSameOpcodeHands()
2886 MachineInstr *RightHandInst = getDefIgnoringCopies(RHSReg, MRI); in matchHoistLogicOpWithSameOpcodeHands()
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