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Searched refs:REG_READ (Results 1 – 25 of 46) sorted by relevance

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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr_clk.c61 regs->CLK0_CLK8_CURRENT_CNT = REG_READ(CLK0_CLK8_CURRENT_CNT) / 10; //dcf clk in rv1_dump_clk_registers()
63 bypass->dcfclk_bypass = REG_READ(CLK0_CLK8_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
68 regs->CLK0_CLK8_DS_CNTL = REG_READ(CLK0_CLK8_DS_CNTL) / 10; //dcf deep sleep divider in rv1_dump_clk_registers()
70 regs->CLK0_CLK8_ALLOW_DS = REG_READ(CLK0_CLK8_ALLOW_DS); //dcf deep sleep allow in rv1_dump_clk_registers()
72 regs->CLK0_CLK10_CURRENT_CNT = REG_READ(CLK0_CLK10_CURRENT_CNT) / 10; //dpref clk in rv1_dump_clk_registers()
74 bypass->dispclk_pypass = REG_READ(CLK0_CLK10_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
78 regs->CLK0_CLK11_CURRENT_CNT = REG_READ(CLK0_CLK11_CURRENT_CNT) / 10; //disp clk in rv1_dump_clk_registers()
80 bypass->dprefclk_bypass = REG_READ(CLK0_CLK11_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
H A Damdgpu_rv1_clk_mgr_vbios_smu.c90 return REG_READ(MP1_SMN_C2PMSG_83); in rv1_vbios_smu_send_msg_with_param()
106 actual_dispclk_set_mhz = REG_READ(MP1_SMN_C2PMSG_83) * 1000; in rv1_vbios_smu_set_dispclk()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
H A Damdgpu_dcn20_hubbub.c495 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A); in hubbub2_wm_read_state()
497 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A); in hubbub2_wm_read_state()
499 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); in hubbub2_wm_read_state()
500 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); in hubbub2_wm_read_state()
502 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A); in hubbub2_wm_read_state()
506 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B); in hubbub2_wm_read_state()
508 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B); in hubbub2_wm_read_state()
510 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B); in hubbub2_wm_read_state()
511 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B); in hubbub2_wm_read_state()
513 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B); in hubbub2_wm_read_state()
[all …]
H A Damdgpu_dcn20_dpp.c71 s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12); in dpp20_read_state()
72 s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14); in dpp20_read_state()
73 s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22); in dpp20_read_state()
74 s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24); in dpp20_read_state()
75 s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32); in dpp20_read_state()
76 s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34); in dpp20_read_state()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
H A Damdgpu_dce_abm.c99 pwm_period_cntl = REG_READ(BL_PWM_PERIOD_CNTL); in calculate_16_bit_backlight_from_pwm()
103 bl_pwm_cntl = REG_READ(BL_PWM_CNTL); in calculate_16_bit_backlight_from_pwm()
242 s2 = REG_READ(BIOS_SCRATCH_2); in dmcu_set_backlight_level()
299 unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL); in dce_abm_get_current_backlight()
310 unsigned int backlight = REG_READ(BL1_PWM_TARGET_ABM_LEVEL); in dce_abm_get_target_backlight()
349 REG_READ(BL_PWM_CNTL); in dce_abm_immediate_disable()
351 REG_READ(BL_PWM_CNTL2); in dce_abm_immediate_disable()
353 REG_READ(BL_PWM_PERIOD_CNTL); in dce_abm_immediate_disable()
391 REG_READ(BL_PWM_CNTL); in dce_abm_init_backlight()
393 REG_READ(BL_PWM_CNTL2); in dce_abm_init_backlight()
[all …]
H A Damdgpu_dce_dmcu.c122 *psr_state = REG_READ(DMCU_IRAM_RD_DATA); in dce_get_dmcu_psr_state()
347 dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA); in dcn10_get_dmcu_version()
348 dmcu->dmcu_version.abm_version = REG_READ(DMCU_IRAM_RD_DATA); in dcn10_get_dmcu_version()
349 dmcu->dmcu_version.psr_version = REG_READ(DMCU_IRAM_RD_DATA); in dcn10_get_dmcu_version()
350 dmcu->dmcu_version.build_version = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) | in dcn10_get_dmcu_version()
351 REG_READ(DMCU_IRAM_RD_DATA)); in dcn10_get_dmcu_version()
393 dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH); in dcn10_dmcu_init()
420 dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH); in dcn10_dmcu_init()
451 uint32_t dmcub_psp_version = REG_READ(DMCUB_SCRATCH15); in dcn21_dmcu_init()
524 *psr_state = REG_READ(DMCU_IRAM_RD_DATA); in dcn10_get_dmcu_psr_state()
H A Damdgpu_dce_aux.c97 uint32_t value = REG_READ(AUX_ARB_CONTROL); in is_engine_available()
110 uint32_t value = REG_READ(AUX_ARB_CONTROL); in acquire_engine()
118 value = REG_READ(AUX_CONTROL); in acquire_engine()
163 value = REG_READ(AUX_ARB_CONTROL); in acquire_engine()
351 value = REG_READ(AUX_SW_STATUS); in get_channel_status()
H A Damdgpu_dce_stream_encoder.c107 regval = REG_READ(AFMT_VBI_PACKET_CONTROL); in dce110_update_generic_info_packet()
351 misc1 = REG_READ(DP_MSA_MISC); in dce110_stream_encoder_dp_set_stream_attribute()
894 value = REG_READ(DP_SEC_CNTL); in dce110_stream_encoder_update_dp_info_packets()
920 value = REG_READ(DP_SEC_CNTL); in dce110_stream_encoder_stop_dp_info_packets()
1537 value = REG_READ(DP_SEC_CNTL); in dce110_se_disable_dp_audio()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
H A Damdgpu_dcn10_hubbub.c59 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A); in hubbub1_wm_read_state()
60 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A); in hubbub1_wm_read_state()
62 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); in hubbub1_wm_read_state()
63 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); in hubbub1_wm_read_state()
65 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A); in hubbub1_wm_read_state()
69 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B); in hubbub1_wm_read_state()
70 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B); in hubbub1_wm_read_state()
72 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B); in hubbub1_wm_read_state()
73 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B); in hubbub1_wm_read_state()
75 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B); in hubbub1_wm_read_state()
[all …]
H A Damdgpu_dcn10_dpp.c118 s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12); in dpp_read_state()
119 s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14); in dpp_read_state()
120 s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22); in dpp_read_state()
121 s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24); in dpp_read_state()
122 s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32); in dpp_read_state()
123 s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34); in dpp_read_state()
H A Damdgpu_dcn10_stream_encoder.c95 regval = REG_READ(AFMT_VBI_PACKET_CONTROL); in enc1_update_generic_info_packet()
315 misc1 = REG_READ(DP_MSA_MISC); in enc1_stream_encoder_dp_set_stream_attribute()
754 value = REG_READ(DP_SEC_CNTL); in enc1_stream_encoder_update_dp_info_packets()
848 value = REG_READ(DP_SEC_CNTL); in enc1_stream_encoder_send_immediate_sdp_message()
875 value = REG_READ(DP_SEC_CNTL); in enc1_stream_encoder_stop_dp_info_packets()
1474 value = REG_READ(DP_SEC_CNTL); in enc1_se_disable_dp_audio()
/netbsd-src/sys/arch/mips/adm5120/
H A Dadm5120_intr.c158 #define REG_READ(o) *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(ADM5120_BASE_ICU + (o))) macro
159 #define REG_WRITE(o,v) (REG_READ(o)) = (v)
220 REG_READ(ICU_MODE_REG) | irqmask); in adm5120_intr_establish()
223 REG_READ(ICU_MODE_REG) & ~irqmask); in adm5120_intr_establish()
275 irqstat = REG_READ(ICU_FIQ_STATUS_REG); in evbmips_iointr()
277 irqstat = REG_READ(ICU_STATUS_REG); in evbmips_iointr()
/netbsd-src/sys/arch/mips/adm5120/dev/
H A Dif_admsw.c164 #define REG_READ(o) bus_space_read_4(sc->sc_st, sc->sc_ioh, (o)) macro
254 REG_READ(PORT_CONF0_REG) | PORT_CONF0_DP_MASK); in admsw_reset()
256 REG_READ(CPUP_CONF_REG) | CPUP_CONF_DCPUP); in admsw_reset()
267 REG_READ(PHY_CNTL2_REG) & ~PHY_CNTL2_PHYR_MASK); in admsw_reset()
284 REG_READ(PHY_CNTL2_REG) | PHY_CNTL2_ANE_MASK | in admsw_reset()
287 REG_WRITE(PHY_CNTL3_REG, REG_READ(PHY_CNTL3_REG) | PHY_CNTL3_RNT); in admsw_reset()
302 REG_READ(FC_TH_REG) & ~(FC_TH_FCS_MASK | FC_TH_D2S_MASK)); in admsw_reset()
316 while (!(REG_READ(MAC_WT0_REG) & MAC_WT0_WRITE_DONE)) in admsw_reset()
319 wdog1 = REG_READ(ADM5120_WDOG1); in admsw_reset()
802 pending = REG_READ(ADMSW_INT_ST); in admsw_intr()
[all …]
H A Duart.c54 #define REG_READ(o) bus_space_read_4(sc->sc_st, sc->sc_ioh, (o)) macro
339 if (REG_READ(UART_RSR_REG) & UART_RSR_BE) { in uart_intr()
344 while ((REG_READ(UART_FR_REG) & UART_FR_RX_FIFO_EMPTY) == 0) { in uart_intr()
345 c = REG_READ(UART_DR_REG) & 0xff; in uart_intr()
H A Dahci.c244 #define REG_READ(o) bus_space_read_4(sc->sc_st, sc->sc_ioh, (o)) macro
294 while (REG_READ(ADMHCD_REG_CONTROL) & ADMHCD_SW_RESET) in ahci_attach()
464 if ((REG_READ(ADMHCD_REG_PORTSTATUS0) & ADMHCD_CCS) != p0_state) { in ahci_poll_hub()
467 p0_state=(REG_READ(ADMHCD_REG_PORTSTATUS0) & ADMHCD_CCS); in ahci_poll_hub()
469 if ((REG_READ(ADMHCD_REG_PORTSTATUS1) & ADMHCD_CCS) != p1_state) { in ahci_poll_hub()
472 p1_state=(REG_READ(ADMHCD_REG_PORTSTATUS1) & ADMHCD_CCS); in ahci_poll_hub()
677 status = REG_READ(ADMHCD_REG_PORTSTATUS0+(index-1)*4); in ahci_roothub_ctrl()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/
H A Damdgpu_rn_clk_mgr.c236 internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT); in rn_dump_clk_registers_internal()
237 internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL); in rn_dump_clk_registers_internal()
239 internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL); //dcf deep sleep divider in rn_dump_clk_registers_internal()
240 internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS); in rn_dump_clk_registers_internal()
242 internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT); in rn_dump_clk_registers_internal()
243 internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL); in rn_dump_clk_registers_internal()
245 internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT); in rn_dump_clk_registers_internal()
246 internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL); in rn_dump_clk_registers_internal()
248 internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT); in rn_dump_clk_registers_internal()
249 internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL); in rn_dump_clk_registers_internal()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/
H A Damdgpu_dmub_dcn21.c63 return (REG_READ(DMCUB_SCRATCH0) == 3); in dmub_dcn21_is_auto_load_done()
68 return REG_READ(DMCUB_SCRATCH10) == 0; in dmub_dcn21_is_phy_init()
H A Damdgpu_dmub_dcn20.c204 return REG_READ(DMCUB_INBOX1_RPTR); in dmub_dcn20_get_inbox1_rptr()
214 return REG_READ(DMCUB_REGION3_CW2_BASE_ADDRESS) != 0; in dmub_dcn20_is_hw_init()
/netbsd-src/sys/dev/goldfish/
H A Dgfpic.c54 #define REG_READ(sc, r) \ macro
106 return ffs(REG_READ(sc, GFPIC_PENDING)) - 1; in gfpic_pending()
H A Dgftty.c78 #define REG_READ(sc, r) REG_READ0((sc)->sc_config, (r)) macro
311 while ((count = REG_READ(sc, GFTTY_BYTES_READY)) != 0) { in gftty_flush()
342 count = REG_READ(sc, GFTTY_BYTES_READY); in gftty_rx()
/netbsd-src/sys/arch/virt68k/dev/
H A Dvirtctrl.c64 #define REG_READ(sc, r) \ macro
113 feat = REG_READ(sc, VIRTCTRL_REG_FEATURES); in virtctrl_attach()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/bios/
H A Damdgpu_bios_parser_helper.c91 active_disp = REG_READ(BIOS_SCRATCH_3) & 0XFFFF; in bios_get_vga_enabled_displays()
/netbsd-src/external/gpl3/binutils/dist/opcodes/
H A Darc-ext.h74 REG_READ, enumerator
/netbsd-src/external/gpl3/binutils.old/dist/opcodes/
H A Darc-ext.h74 REG_READ, enumerator
/netbsd-src/sys/external/isc/atheros_hal/dist/ar5312/
H A Dar5312reg.h32 #define REG_READ(_reg) *((volatile uint32_t *)(_reg)) macro

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