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Searched refs:REG_FIELD_PREP (Results 1 – 4 of 4) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/
H A Dintel_lvds.c218 REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | in intel_lvds_pps_init_hw()
219 REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | in intel_lvds_pps_init_hw()
220 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5)); in intel_lvds_pps_init_hw()
223 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | in intel_lvds_pps_init_hw()
224 REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx)); in intel_lvds_pps_init_hw()
227 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | in intel_lvds_pps_init_hw()
228 REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, in intel_lvds_pps_init_hw()
H A Dintel_dp.c6914 pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) | in intel_dp_init_panel_power_sequencer_registers()
6915 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8); in intel_dp_init_panel_power_sequencer_registers()
6916 pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) | in intel_dp_init_panel_power_sequencer_registers()
6917 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10); in intel_dp_init_panel_power_sequencer_registers()
6950 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | in intel_dp_init_panel_power_sequencer_registers()
6951 REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000))); in intel_dp_init_panel_power_sequencer_registers()
6957 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)); in intel_dp_init_panel_power_sequencer_registers()
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/
H A Di915_reg.h165 #define REG_FIELD_PREP(__mask, __val) \ macro
4879 #define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0)
4880 #define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1)
4881 #define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2)
4884 #define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0)
4885 #define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1)
4886 #define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2)
4887 #define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3)
4888 #define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8)
4889 #define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9)
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/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/gt/uc/
H A Dintel_guc.c147 u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST); in gen11_enable_guc_interrupts()