Searched refs:RC0 (Results 1 – 3 of 3) sorted by relevance
238 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0); in runOnMachineFunction() local239 if (RC0->getID() == Hexagon::PredRegsRegClassID) { in runOnMachineFunction()
822 const TargetRegisterClass *RC0 = MRI->getRegClass(PHIRes); in processPHINode() local823 if (AllAGPRUses && numVGPRUses && !TRI->hasAGPRs(RC0)) { in processPHINode()825 MRI->setRegClass(PHIRes, TRI->getEquivalentAGPRClass(RC0)); in processPHINode()870 RC0 != &AMDGPU::VReg_1RegClass) && in processPHINode()
1190 const TargetRegisterClass &RC0 = *MRI->getRegClass(Reg0); in allocateInstruction() local1195 unsigned ClassSize0 = RegClassInfo.getOrder(&RC0).size(); in allocateInstruction()1198 bool SmallClass0 = ClassSize0 < RegClassDefCounts[RC0.getID()]; in allocateInstruction()