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Searched refs:R29 (Results 1 – 25 of 29) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonPseudo.td81 let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in
85 let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
312 let Defs = [R29], hasSideEffects = 1 in
353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
359 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
368 let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
374 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
383 let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in {
H A DHexagonRegisterInfo.cpp150 Reserved.set(Hexagon::R29); in getReservedRegs()
416 return Hexagon::R29; in getStackRegister()
H A DHexagonRegisterInfo.td106 def R29 : Ri<29, "r29", ["sp"]>, DwarfRegNum<[29]>;
126 def D14 : Rd<28, "r29:28", [R28, R29]>, DwarfRegNum<[60]>;
374 R10, R11, R29, R30, R31)>;
H A DHexagonDepInstrInfo.td4892 let Uses = [R29];
4919 let Uses = [R29];
4940 let Uses = [R29];
4957 let Uses = [R29];
4974 let Uses = [R29];
4994 let Uses = [R29];
8850 let Defs = [R29];
13500 let Defs = [PC, R29];
13524 let Defs = [PC, R29];
13547 let Defs = [PC, R29];
[all …]
H A DHexagonISelLowering.cpp298 .Case("r29", Hexagon::R29) in getRegisterByName()
317 .Case("sp", Hexagon::R29) in getRegisterByName()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp207 Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) { in getDuplexCandidateGroup()
263 HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg && in getDuplexCandidateGroup()
326 Hexagon::R29 == Src1Reg && inRange<5, 2>(MCI, 1)) { in getDuplexCandidateGroup()
370 HexagonMCInstrInfo::isIntReg(Src1Reg) && Hexagon::R29 == Src1Reg && in getDuplexCandidateGroup()
418 if (HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg && in getDuplexCandidateGroup()
725 if (Inst.getOperand(1).getReg() == Hexagon::R29) { in deriveSubInst()
878 if (Inst.getOperand(1).getReg() == Hexagon::R29) { in deriveSubInst()
935 } else if (Inst.getOperand(0).getReg() == Hexagon::R29) { in deriveSubInst()
943 if (Inst.getOperand(0).getReg() == Hexagon::R29) { in deriveSubInst()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td73 def R29 : AVRReg<29, "r29", [], ["yh"]>, DwarfRegNum<[29]>;
90 def R29R28 : AVRReg<28, "r29:r28", [R28, R29], ["Y"]>, DwarfRegNum<[28]>;
131 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
149 R28, R29, R17, R16
H A DAVRCallingConv.td40 def CSR_Normal : CalleeSavedRegs<(add R29, R28, (sequence "R%u", 17, 2))>;
H A DAVRRegisterInfo.cpp79 Reserved.set(AVR::R29); in getReservedRegs()
H A DAVRFrameLowering.cpp409 SavedRegs.set(AVR::R29); in determineCalleeSaves()
H A DAVRISelLowering.cpp2086 .Case("r27", AVR::R27).Case("r28", AVR::R28).Case("r29", AVR::R29) in getRegisterByName()
/netbsd-src/external/bsd/pcc/dist/pcc/arch/powerpc/
H A Dmacdefs.h176 #define R29 29 macro
326 { R26, R27, -1 }, { R28, R29, -1 }, \
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiBaseInfo.h107 case Lanai::R29: in getLanaiRegisterNumbering()
/netbsd-src/external/gpl3/gcc/dist/libgcc/config/avr/libf7/
H A Dasm-defs.h123 R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, \
/netbsd-src/external/gpl3/gcc.old/dist/libgcc/config/avr/libf7/
H A Dasm-defs.h123 R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, \
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp160 Lanai::R24, Lanai::R25, Lanai::R26, Lanai::R27, Lanai::R28, Lanai::R29,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/Disassembler/
H A DAVRDisassembler.cpp68 AVR::R28, AVR::R29, AVR::R30, AVR::R31,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.td273 R28, R29, R30, R31, CR2, CR3, CR4
289 R29, R30, R31, F14, F15, F16, F17, F18,
H A DPPCRegisterInfo.cpp338 markSuperRegs(Reserved, PPC::R29); in getReservedRegs()
1381 return PPC::R29; in getBaseRegister()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp204 if (MI.getOperand(0).getReg() == Hexagon::R29) { in remapInstruction()
553 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29, in DecodeIntRegsRegisterClass()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td81 def R29 : CSKYReg<29, "r29", ["rtb"]>, DwarfRegNum<[29]>;
/netbsd-src/sys/external/bsd/gnu-efi/dist/inc/
H A Defidebug.h357 UINT64 R29; member
/netbsd-src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/ti/
H A Dk3-j721e-common-proc-board.dts123 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
/netbsd-src/external/gpl3/gcc.old/dist/libgcc/config/avr/
H A Dlib1funcs.S1274 ;; Save 10 Registers: R10..R17, R28, R29
/netbsd-src/external/gpl3/gcc/dist/libgcc/config/avr/
H A Dlib1funcs.S1274 ;; Save 10 Registers: R10..R17, R28, R29

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