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Searched refs:R2 (Results 1 – 25 of 1148) sorted by relevance

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/netbsd-src/sys/arch/amiga/dev/
H A Dwstsc.c379 #define R2 (*buf++ = *sci_dma) in wstsc_dma_xfer_in2() macro
380 R2; R2; R2; R2; R2; R2; R2; R2; in wstsc_dma_xfer_in2()
381 R2; R2; R2; R2; R2; R2; R2; R2; in wstsc_dma_xfer_in2()
382 R2; R2; R2; R2; R2; R2; R2; R2; in wstsc_dma_xfer_in2()
383 R2; R2; R2; R2; R2; R2; R2; R2; in wstsc_dma_xfer_in2()
384 R2; R2; R2; R2; R2; R2; R2; R2; in wstsc_dma_xfer_in2()
385 R2; R2; R2; R2; R2; R2; R2; R2; in wstsc_dma_xfer_in2()
386 R2; R2; R2; R2; R2; R2; R2; R2; in wstsc_dma_xfer_in2()
387 R2; R2; R2; R2; R2; R2; R2; R2; in wstsc_dma_xfer_in2()
/netbsd-src/external/gpl3/gdb/dist/sim/testsuite/bfin/
H A Dc_dsp32alu_rrppmm.s21 R2 = R0 +|+ R2, R5 = R0 -|- R2; define
24 R5 = R0 +|+ R5, R2 = R0 -|- R5;
46 R2 = R1 +|+ R2, R5 = R1 -|- R2; define
49 R5 = R1 +|+ R5, R2 = R1 -|- R5;
69 R0 = R2 +|+ R0, R7 = R2 -|- R0;
70 R1 = R2 +|+ R1, R6 = R2 -|- R1;
71 R2 = R2 +|+ R2, R5 = R2 -|- R2; define
72 R3 = R2 +|+ R3, R4 = R2 -|- R3;
73 R4 = R2 +|+ R4, R3 = R2 -|- R4;
74 R5 = R2 +|+ R5, R2 = R2 -|- R5;
[all …]
H A Dc_dsp32alu_rrpmmp.s21 R2 = R0 +|- R2 , R5 = R0 -|+ R2; define
24 R5 = R0 +|- R5 , R2 = R0 -|+ R5;
46 R2 = R1 +|- R2 , R5 = R1 -|+ R2; define
49 R5 = R1 +|- R5 , R2 = R1 -|+ R5;
69 R0 = R2 +|- R0 , R7 = R2 -|+ R0;
70 R1 = R2 +|- R1 , R6 = R2 -|+ R1;
71 R2 = R2 +|- R2 , R5 = R2 -|+ R2; define
72 R3 = R2 +|- R3 , R4 = R2 -|+ R3;
73 R4 = R2 +|- R4 , R3 = R2 -|+ R4;
74 R5 = R2 +|- R5 , R2 = R2 -|+ R5;
[all …]
H A Dc_dsp32alu_rrpmmp_sft.s22 R2 = R0 +|- R2 , R5 = R0 -|+ R2 (ASR); define
25 R5 = R0 +|- R5 , R2 = R0 -|+ R5 (ASR);
47 R2 = R1 +|- R2 , R5 = R1 -|+ R2 (ASR); define
50 R5 = R1 +|- R5 , R2 = R1 -|+ R5 (ASR);
70 R0 = R2 +|- R0 , R7 = R2 -|+ R0 (ASR);
71 R1 = R2 +|- R1 , R6 = R2 -|+ R1 (ASR);
72 R2 = R2 +|- R2 , R5 = R2 -|+ R2 (ASR); define
73 R3 = R2 +|- R3 , R4 = R2 -|+ R3 (ASR);
74 R4 = R2 +|- R4 , R3 = R2 -|+ R4 (ASR);
75 R5 = R2 +|- R5 , R2 = R2 -|+ R5 (ASR);
[all …]
H A Dc_dsp32alu_rrppmm_sft.s21 R2 = R0 +|+ R2, R5 = R0 -|- R2 (ASR); define
24 R5 = R0 +|+ R5, R2 = R0 -|- R5 (ASR);
46 R2 = R1 +|+ R2, R5 = R1 -|- R2 (ASL); define
49 R5 = R1 +|+ R5, R2 = R1 -|- R5 (ASR);
69 R0 = R2 +|+ R0, R7 = R2 -|- R0 (ASR);
70 R1 = R2 +|+ R1, R6 = R2 -|- R1 (ASR);
71 R2 = R2 +|+ R2, R5 = R2 -|- R2 (ASR); define
72 R3 = R2 +|+ R3, R4 = R2 -|- R3 (ASL);
73 R4 = R2 +|+ R4, R3 = R2 -|- R4 (ASR);
74 R5 = R2 +|+ R5, R2 = R2 -|- R5 (ASR);
[all …]
H A Dc_dsp32alu_rrpm.s21 R2 = R0 + R2, R5 = R0 - R2 (NS); define
24 R5 = R0 + R5, R2 = R0 - R5 (NS);
46 R2 = R1 + R2, R5 = R1 - R2 (NS); define
49 R5 = R1 + R5, R2 = R1 - R5 (NS);
70 R0 = R2 + R0, R7 = R2 - R0 (NS);
71 R1 = R2 + R1, R6 = R2 - R1 (NS);
72 R2 = R2 + R2, R5 = R2 - R2 (NS); define
73 R3 = R2 + R3, R4 = R2 - R3 (NS);
74 R4 = R2 + R4, R3 = R2 - R4 (NS);
75 R5 = R2 + R5, R2 = R2 - R5 (NS);
[all …]
H A Dc_dsp32alu_rrppmm_sft_x.s21 R2 = R0 +|+ R2, R5 = R0 -|- R2 (CO , ASR); define
24 R5 = R0 +|+ R5, R2 = R0 -|- R5 (CO , ASR);
46 R2 = R1 +|+ R2, R5 = R1 -|- R2 (CO , ASL); define
49 R5 = R1 +|+ R5, R2 = R1 -|- R5 (CO , ASR);
69 R0 = R2 +|+ R0, R7 = R2 -|- R0 (CO , ASR);
70 R1 = R2 +|+ R1, R6 = R2 -|- R1 (CO , ASR);
71 R2 = R2 +|+ R2, R5 = R2 -|- R2 (CO , ASR); define
72 R3 = R2 +|+ R3, R4 = R2 -|- R3 (CO , ASL);
73 R4 = R2 +|+ R4, R3 = R2 -|- R4 (CO , ASR);
74 R5 = R2 +|+ R5, R2 = R2 -|- R5 (CO , ASR);
[all …]
H A Dc_dsp32alu_rrpmmp_sft_x.s21 R2 = R0 +|- R2 , R5 = R0 -|+ R2 (CO , ASR); define
24 R5 = R0 +|- R5 , R2 = R0 -|+ R5 (CO , ASR);
46 R2 = R1 +|- R2 , R5 = R1 -|+ R2 (CO , ASR); define
49 R5 = R1 +|- R5 , R2 = R1 -|+ R5 (CO , ASR);
69 R0 = R2 +|- R0 , R7 = R2 -|+ R0 (CO , ASR);
70 R1 = R2 +|- R1 , R6 = R2 -|+ R1 (CO , ASR);
71 R2 = R2 +|- R2 , R5 = R2 -|+ R2 (CO , ASR); define
72 R3 = R2 +|- R3 , R4 = R2 -|+ R3 (CO , ASR);
73 R4 = R2 +|- R4 , R3 = R2 -|+ R4 (CO , ASR);
74 R5 = R2 +|- R5 , R2 = R2 -|+ R5 (CO , ASR);
[all …]
H A Dx1.s10 R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR); define
16 R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR); define
20 R0 = R2 +|+ R3, R1 = R2 -|- R3 (S , ASR);
32 R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR); define
37 R2 = R2 +|+ R4, R3 = R2 -|- R4 (S , ASR); define
41 R2 = R2 +|+ R3, R3 = R2 -|- R3 (S , ASR); define
45 R4 = R2 +|+ R2, R5 = R2 -|- R2 (ASL);
49 R2 = R2 +|+ R2, R3 = R2 -|- R2 (S , ASL); define
56 R2 = R0 +|+ R1, R3 = R0 -|- R1 (S, ASL); define
65 R2 = R0 +|+ R1, R3 = R0 -|- R1 (S, ASL); define
[all …]
H A Ddsp_d1.s11 loadsym R2, foo;
16 R1 = R7 - R2
21 R1 = R7 - R2;
25 R1 = R7 - R2
30 loadsym R2, foo;
35 R1 = R7 - R2
39 R1 = R7 - R2
43 R1 = R7 - R2;
47 R1 = R7 - R2;
51 R1 = R7 - R2;
[all …]
H A Dc_comp3op_dr_plus_dr.s21 R2 = R0 + R2; define
46 R2 = R1 + R2; define
69 R0 = R2 + R0;
70 R1 = R2 + R1;
71 R2 = R2 + R2; define
72 R3 = R2 + R3;
73 R4 = R2 + R4;
74 R5 = R2 + R5;
75 R6 = R2 + R6;
76 R7 = R2 + R7;
[all …]
H A Dc_comp3op_dr_minus_dr.s21 R2 = R0 - R2; define
46 R2 = R1 - R2; define
69 R0 = R2 - R0;
70 R1 = R2 - R1;
71 R2 = R2 - R2; define
72 R3 = R2 - R3;
73 R4 = R2 - R4;
74 R5 = R2 - R5;
75 R6 = R2 - R6;
76 R7 = R2 - R7;
[all …]
H A Dc_comp3op_dr_or_dr.s21 R2 = R0 | R2; define
46 R2 = R1 | R2; define
69 R0 = R2 | R0;
70 R1 = R2 | R1;
71 R2 = R2 | R2; define
72 R3 = R2 | R3;
73 R4 = R2 | R4;
74 R5 = R2 | R5;
75 R6 = R2 | R6;
76 R7 = R2 | R7;
[all …]
H A Dc_comp3op_dr_xor_dr.s21 R2 = R0 ^ R2; define
46 R2 = R1 ^ R2; define
69 R0 = R2 ^ R0;
70 R1 = R2 ^ R1;
71 R2 = R2 ^ R2; define
72 R3 = R2 ^ R3;
73 R4 = R2 ^ R4;
74 R5 = R2 ^ R5;
75 R6 = R2 ^ R6;
76 R7 = R2 ^ R7;
[all …]
H A Dc_comp3op_dr_and_dr.s21 R2 = R0 & R2; define
46 R2 = R1 & R2; define
69 R0 = R2 & R0;
70 R1 = R2 & R1;
71 R2 = R2 & R2; define
72 R3 = R2 & R3;
73 R4 = R2 & R4;
74 R5 = R2 & R5;
75 R6 = R2 & R6;
76 R7 = R2 & R7;
[all …]
H A Dc_dsp32mult_dr.s22 R2.H = R1.L * R0.L, R2.L = R1.H * R0.L;
41 R4.H = R2.L * R2.H, R4.L = R2.H * R2.L;
42 R5.H = R2.L * R3.H, R5.L = R2.H * R3.H;
43 R6.H = R3.L * R2.H, R6.L = R3.L * R2.L;
45 R2.H = R2.L * R2.H, R2.L = R2.H * R2.L;
46 R3.H = R2.L * R3.H, R3.L = R2.H * R3.H;
47 R0.H = R3.L * R2.H, R0.L = R3.L * R2.L;
68 R2.H = R5.H * R4.L, R2.L = R5.H * R4.L;
94 R2.H = R7.H * R6.H, R2.L = R7.H * R6.L;
120 R2.H = R2.H * R5.L, R2.L = R2.L * R5.L;
[all …]
H A Dc_dsp32alu_rmm.s24 R2 = R0 -|- R2; define
49 R2 = R1 -|- R2; define
72 R0 = R2 -|- R0;
73 R1 = R2 -|- R1;
74 R2 = R2 -|- R2; define
75 R3 = R2 -|- R3;
76 R4 = R2 -|- R4;
77 R5 = R2 -|- R5;
78 R6 = R2 -|- R6;
79 R7 = R2 -|- R7;
[all …]
H A Dc_dsp32alu_rpm.s24 R2 = R0 +|- R2; define
49 R2 = R1 +|- R2; define
72 R0 = R2 +|- R0;
73 R1 = R2 +|- R1;
74 R2 = R2 +|- R2; define
75 R3 = R2 +|- R3;
76 R4 = R2 +|- R4;
77 R5 = R2 +|- R5;
78 R6 = R2 +|- R6;
79 R7 = R2 +|- R7;
[all …]
H A Dc_dsp32alu_rpp.s24 R2 = R0 +|+ R2; define
49 R2 = R1 +|+ R2; define
72 R0 = R2 +|+ R0;
73 R1 = R2 +|+ R1;
74 R2 = R2 +|+ R2; define
75 R3 = R2 +|+ R3;
76 R4 = R2 +|+ R4;
77 R5 = R2 +|+ R5;
78 R6 = R2 +|+ R6;
79 R7 = R2 +|+ R7;
[all …]
/netbsd-src/external/gpl3/binutils/dist/opcodes/
H A Dia64-opc-a.c93 {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 0), {R1, R2, R3}, EMPTY},
94 {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 1), {R1, R2, R3, C1}, EMPTY},
95 {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 1), {R1, R2, R3}, EMPTY},
96 {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 0), {R1, R2, R3, C1}, EMPTY},
97 {"addp4", A, OpX2aVeX4X2b (8, 0, 0, 2, 0), {R1, R2, R3}, EMPTY},
98 {"and", A, OpX2aVeX4X2b (8, 0, 0, 3, 0), {R1, R2, R3}, EMPTY},
99 {"andcm", A, OpX2aVeX4X2b (8, 0, 0, 3, 1), {R1, R2, R3}, EMPTY},
100 {"or", A, OpX2aVeX4X2b (8, 0, 0, 3, 2), {R1, R2, R3}, EMPTY},
101 {"xor", A, OpX2aVeX4X2b (8, 0, 0, 3, 3), {R1, R2, R3}, EMPTY},
102 {"shladd", A, OpX2aVeX4 (8, 0, 0, 4), {R1, R2, CNT2a, R3}, EMPTY},
[all …]
H A Dv850-opc.c984 #define R2 (R1_PERCENT + 1) macro
988 #define R2_NOTR0 (R2 + 1)
1284 #define IF1 {R1, R2}
1287 #define IF2 {I5, R2}
1293 #define IF6 {I16, R1, R2}
1296 #define IF6U {I16U, R1, R2}
1340 { "adf", two (0x07e0, 0x03a0), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, PROCESSOR_V85…
1428 { "bsh", two (0x07e0, 0x0342), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 },
1430 { "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 },
1433 { "bins", two (0x07e0, 0x0090), two (0x07e0, 0x07f1), {R1, POS_U, WIDTH_U, R2}, 0, PROCESSOR_V850…
[all …]
H A Dia64-opc-i.c116 {"chk.s.i", I0, OpX3 (0, 1), {R2, TGT25b}, EMPTY},
118 {"mov", I, OpX3XbIhWhTag13 (0, 7, 0, 0, 1, 0), {B1, R2}, PSEUDO, 0, NULL},
120 I, OpX3XbIhWh (0, a, b, c, d), {B1, R2, TAG13b}, EMPTY
135 {"mov", I, OpX3 (0, 3), {PR, R2, IMM17}, EMPTY},
137 {"mov", I, FULL17 | OpX3 (0, 3) | FULL17, {PR, R2}, PSEUDO, 0, NULL},
141 {"mov.i", I, OpX3X6 (0, 0, 0x2a), {AR3, R2}, EMPTY},
155 {"dep", I, Op (4), {R1, R2, R3, CPOS6c, LEN4}, EMPTY},
157 {"shrp", I, OpX2X (5, 3, 0), {R1, R2, R3, CNT6}, EMPTY},
167 {"shl", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a},
169 {"dep.z", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a, LEN6}, EMPTY},
[all …]
/netbsd-src/external/gpl3/binutils.old/dist/opcodes/
H A Dia64-opc-a.c93 {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 0), {R1, R2, R3}, EMPTY},
94 {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 1), {R1, R2, R3, C1}, EMPTY},
95 {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 1), {R1, R2, R3}, EMPTY},
96 {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 0), {R1, R2, R3, C1}, EMPTY},
97 {"addp4", A, OpX2aVeX4X2b (8, 0, 0, 2, 0), {R1, R2, R3}, EMPTY},
98 {"and", A, OpX2aVeX4X2b (8, 0, 0, 3, 0), {R1, R2, R3}, EMPTY},
99 {"andcm", A, OpX2aVeX4X2b (8, 0, 0, 3, 1), {R1, R2, R3}, EMPTY},
100 {"or", A, OpX2aVeX4X2b (8, 0, 0, 3, 2), {R1, R2, R3}, EMPTY},
101 {"xor", A, OpX2aVeX4X2b (8, 0, 0, 3, 3), {R1, R2, R3}, EMPTY},
102 {"shladd", A, OpX2aVeX4 (8, 0, 0, 4), {R1, R2, CNT2a, R3}, EMPTY},
[all …]
H A Dv850-opc.c984 #define R2 (R1_PERCENT + 1) macro
988 #define R2_NOTR0 (R2 + 1)
1284 #define IF1 {R1, R2}
1287 #define IF2 {I5, R2}
1293 #define IF6 {I16, R1, R2}
1296 #define IF6U {I16U, R1, R2}
1340 { "adf", two (0x07e0, 0x03a0), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, PROCESSOR_V85…
1428 { "bsh", two (0x07e0, 0x0342), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 },
1430 { "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 },
1433 { "bins", two (0x07e0, 0x0090), two (0x07e0, 0x07f1), {R1, POS_U, WIDTH_U, R2}, 0, PROCESSOR_V850…
[all …]
H A Dia64-opc-i.c116 {"chk.s.i", I0, OpX3 (0, 1), {R2, TGT25b}, EMPTY},
118 {"mov", I, OpX3XbIhWhTag13 (0, 7, 0, 0, 1, 0), {B1, R2}, PSEUDO, 0, NULL},
120 I, OpX3XbIhWh (0, a, b, c, d), {B1, R2, TAG13b}, EMPTY
135 {"mov", I, OpX3 (0, 3), {PR, R2, IMM17}, EMPTY},
137 {"mov", I, FULL17 | OpX3 (0, 3) | FULL17, {PR, R2}, PSEUDO, 0, NULL},
141 {"mov.i", I, OpX3X6 (0, 0, 0x2a), {AR3, R2}, EMPTY},
155 {"dep", I, Op (4), {R1, R2, R3, CPOS6c, LEN4}, EMPTY},
157 {"shrp", I, OpX2X (5, 3, 0), {R1, R2, R3, CNT6}, EMPTY},
167 {"shl", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a},
169 {"dep.z", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a, LEN6}, EMPTY},
[all …]

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