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/netbsd-src/external/gpl3/gcc.old/dist/libgcc/config/msp430/
H A Dslli.S122 MOV R11, R15 ; Free up R11 first
123 MOV R12, R11 ; Save the shift amount in R11
127 CMP #0,R11
139 ADD #-1,R11
H A Dsrai.S121 MOV R11, R15 ; Free up R11 first
122 MOV R12, R11 ; Save the shift amount in R11
126 CMP #0, R11
138 ADD #-1,R11
H A Dsrli.S125 MOV R11, R15 ; Free up R11 first
126 MOV R12, R11 ; Save the shift amount in R11
130 CMP #0,R11
143 ADD #-1,R11
/netbsd-src/external/gpl3/gcc/dist/libgcc/config/msp430/
H A Dslli.S137 MOV R11, R15 ; Free up R11 first
138 MOV R12, R11 ; Save the shift amount in R11
142 CMP #0,R11
154 ADD #-1,R11
H A Dsrli.S141 MOV R11, R15 ; Free up R11 first
142 MOV R12, R11 ; Save the shift amount in R11
146 CMP #0,R11
159 ADD #-1,R11
H A Dsrai.S136 MOV R11, R15 ; Free up R11 first
137 MOV R12, R11 ; Save the shift amount in R11
141 CMP #0, R11
153 ADD #-1,R11
/netbsd-src/sys/arch/vax/boot/boot/
H A Dconsio2.S64 ENTRY(ka630_rom_getchar, 0x0802) # save-mask: R1, R11
82 ENTRY(ka630_rom_putchar, 0x802) # save-mask: R1, R11
95 ENTRY(ka53_rom_getchar, 0x0802) # save-mask: R1, R11
114 ENTRY(ka53_rom_putchar, 0x0802) # save-mask: R1, R11
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.td36 def R11 : Ri<11, "r11">, DwarfRegNum<[11]>;
50 R11)>;
56 R11, CP, DP, SP, LR)> {
H A DXCoreCallingConv.td30 // The 'nest' parameter, if any, is passed in R11.
31 CCIfNest<CCAssignToReg<[R11]>>,
H A DXCoreInstrInfo.td638 let Uses = [R11], isCall=1 in
652 let Defs = [R11], hasSideEffects = 0, isReMaterializable = 1 in
656 let Defs = [R11], isReMaterializable = 1 in
658 [(set R11, (cprelwrapper tglobaladdr:$a))]>;
660 let Defs = [R11] in
685 let Defs = [R11], isReMaterializable = 1 in {
690 [(set R11, (pcrelwrapper tglobaladdr:$a))]>;
699 [(set R11, (pcrelwrapper tglobaladdr:$a))]>;
703 [(set R11, (pcrelwrapper tblockaddress:$a))]>;
708 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td36 def RR2 : LanaiReg<11, "rr2", [R11]>, DwarfRegAlias<R11>;
50 R10, RR1, R11, RR2, // programmer controlled registers
/netbsd-src/crypto/external/bsd/openssl/dist/crypto/sha/asm/
H A Dkeccak1600-avx512vl.pl56 my ($R20,$R01,$R31,$R21,$R41,$R11) = map("%ymm$_",(16..21));
110 vprolvq $R11,$A11,@T[1] # $A11 -> future $A01
215 vmovdqa64 5*32(%r8),$R11
301 vmovdqa64 5*32(%r8),$R11
/netbsd-src/crypto/external/bsd/openssl.old/dist/crypto/sha/asm/
H A Dkeccak1600-avx512vl.pl56 my ($R20,$R01,$R31,$R21,$R41,$R11) = map("%ymm$_",(16..21));
110 vprolvq $R11,$A11,@T[1] # $A11 -> future $A01
215 vmovdqa64 5*32(%r8),$R11
301 vmovdqa64 5*32(%r8),$R11
/netbsd-src/external/bsd/pcc/dist/pcc/arch/pdp10/
H A Dmacdefs.h170 #define R11 011 macro
229 { R10, R11, XR7, XR11, -1 }, \
230 { R11, R12, XR10, XR12, -1 }, \
/netbsd-src/external/gpl3/gcc/dist/libgcc/config/rl78/
H A Dfpbit-sf.S30 ;; Output to R8..R11.
272 ;; Input at [SP+4]..[SP+7], result is in (lsb) R8..R11 (msb).
331 ;; Input at [SP+4]..[SP+7], result is in (lsb) R8..R11 (msb)
349 ;; A X R11 R10
353 ;; A X R11 R10
402 ;; H X R11 R10
472 ;; Argument in [SP+4]..[SP+7]. Result in R8..R11.
519 ;; Argument in [SP+4]..[SP+7]. Result in R8..R11.
568 ;; R11 R10 R9 R8
/netbsd-src/external/gpl3/gcc.old/dist/libgcc/config/rl78/
H A Dfpbit-sf.S30 ;; Output to R8..R11.
272 ;; Input at [SP+4]..[SP+7], result is in (lsb) R8..R11 (msb).
331 ;; Input at [SP+4]..[SP+7], result is in (lsb) R8..R11 (msb)
349 ;; A X R11 R10
353 ;; A X R11 R10
402 ;; H X R11 R10
472 ;; Argument in [SP+4]..[SP+7]. Result in R8..R11.
519 ;; Argument in [SP+4]..[SP+7]. Result in R8..R11.
568 ;; R11 R10 R9 R8
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86IndirectThunks.cpp96 BuildMI(&MF.front(), DebugLoc(), TII->get(X86::JMP64r)).addReg(X86::R11); in populateThunk()
97 MF.front().addLiveIn(X86::R11); in populateThunk()
160 ThunkReg = X86::R11; in populateThunk()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMCallingConv.td122 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
270 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
275 def CSR_Win_AAPCS_CFGuard_Check : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7,
286 R11, R10, R9, R8,
297 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
321 def CSR_iOS_CXX_TLS_PE : CalleeSavedRegs<(add LR, R12, R11, R7, R5, R4)>;
340 // FIXME: we mark R11 as callee-saved since it's often the frame-pointer, and
343 def CSR_FIQ : CalleeSavedRegs<(add LR, R11, (sequence "R%u", 7, 0))>;
H A DARMBaseRegisterInfo.h54 case R8: case R9: case R10: case R11: case R12: in isARMArea1Register()
66 case R8: case R9: case R10: case R11: case R12: in isARMArea2Register()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td55 def R11 : AVRReg<11, "r11">, DwarfRegNum<[11]>;
100 def R11R10 : AVRReg<10, "r11:r10", [R10, R11]>, DwarfRegNum<[10]>;
115 def R12R11 : AVRReg<11, "r12:r11", [R11, R12]>, DwarfRegNum<[11]>;
131 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
138 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp53 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
59 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
H A DMSP430RegisterInfo.td66 def R11 : MSP430RegWithSubregs<11, "r11", [R11B]>;
83 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
H A DARCRegisterInfo.td40 def R11 : Core<11, "%r11">, DwarfRegNum<[11]>;
72 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,
/netbsd-src/external/bsd/pcc/dist/pcc/arch/arm/
H A Dmacdefs.h127 #define R11 11 macro
134 #define FP R11
/netbsd-src/external/bsd/pcc/dist/pcc/arch/vax/
H A Dmacdefs.h137 # define R11 11 macro
226 { R10, R11, XR9, -1 },

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