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Searched refs:PtrReg (Results 1 – 9 of 9) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp423 Register PtrReg = B.getMRI()->createGenericVirtualRegister(PtrTy); in lowerParameter() local
424 lowerParameterPtr(PtrReg, B, ParamTy, Offset); in lowerParameter()
432 B.buildLoad(DstReg, PtrReg, *MMO); in lowerParameter()
541 Register PtrReg = MRI.createGenericVirtualRegister(ConstPtrTy); in lowerFormalArgumentsKernel() local
542 lowerParameterPtr(PtrReg, B, ArgTy, ArgOffset); in lowerFormalArgumentsKernel()
544 B.buildAddrSpaceCast(VRegs[i][0], PtrReg); in lowerFormalArgumentsKernel()
H A DAMDGPURegisterBankInfo.cpp1165 Register PtrReg = MI.getOperand(1).getReg(); in applyMappingLoad() local
1176 auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0); in applyMappingLoad()
1180 auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0); in applyMappingLoad()
1184 B.buildLoadFromOffset(MI.getOperand(0), PtrReg, *MMO, 0); in applyMappingLoad()
1191 auto Load0 = B.buildLoadFromOffset(Part64, PtrReg, *MMO, 0); in applyMappingLoad()
1192 auto Load1 = B.buildLoadFromOffset(Part32, PtrReg, *MMO, 8); in applyMappingLoad()
1199 auto WideLoad = B.buildLoadFromOffset(WiderTy, PtrReg, *MMO, 0); in applyMappingLoad()
3204 Register PtrReg) const { in getValueMappingForPtr()
3205 LLT PtrTy = MRI.getType(PtrReg); in getValueMappingForPtr()
3213 const RegisterBank *PtrBank = getRegBank(PtrReg, MRI, *TRI); in getValueMappingForPtr()
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H A DAMDGPULegalizerInfo.cpp2397 Register PtrReg = MI.getOperand(1).getReg(); in legalizeLoad() local
2398 LLT PtrTy = MRI.getType(PtrReg); in legalizeLoad()
2403 auto Cast = B.buildAddrSpaceCast(ConstPtr, PtrReg); in legalizeLoad()
2444 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0); in legalizeLoad()
2452 WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0); in legalizeLoad()
2460 B.buildLoadFromOffset(WideLoad, PtrReg, *MMO, 0); in legalizeLoad()
2496 Register PtrReg = MI.getOperand(1).getReg(); in legalizeAtomicCmpXChg() local
2500 assert(AMDGPU::isFlatGlobalAddrSpace(MRI.getType(PtrReg).getAddressSpace()) && in legalizeAtomicCmpXChg()
2510 .addUse(PtrReg) in legalizeAtomicCmpXChg()
H A DAMDGPUInstructionSelector.cpp2371 Register PtrReg = MI.getOperand(1).getReg(); in selectG_AMDGPU_ATOMIC_CMPXCHG() local
2372 const LLT PtrTy = MRI->getType(PtrReg); in selectG_AMDGPU_ATOMIC_CMPXCHG()
3383 unsigned PtrReg = GEPInfo.SgprParts[0]; in selectSmrdImm() local
3385 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); }, in selectSmrdImm()
3399 Register PtrReg = GEPInfo.SgprParts[0]; in selectSmrdImm32() local
3406 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); }, in selectSmrdImm32()
3433 Register PtrReg = GEPInfo.SgprParts[0]; in selectSmrdSgpr() local
3438 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); }, in selectSmrdSgpr()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp2314 MachineInstr &MI, std::pair<Register, bool> &PtrReg) { in matchCombineAddP2IToPtrAdd() argument
2322 PtrReg.second = false; in matchCombineAddP2IToPtrAdd()
2324 if (mi_match(SrcReg, MRI, m_GPtrToInt(m_Reg(PtrReg.first)))) { in matchCombineAddP2IToPtrAdd()
2327 LLT PtrTy = MRI.getType(PtrReg.first); in matchCombineAddP2IToPtrAdd()
2332 PtrReg.second = true; in matchCombineAddP2IToPtrAdd()
2339 MachineInstr &MI, std::pair<Register, bool> &PtrReg) { in applyCombineAddP2IToPtrAdd() argument
2344 const bool DoCommute = PtrReg.second; in applyCombineAddP2IToPtrAdd()
2347 LHS = PtrReg.first; in applyCombineAddP2IToPtrAdd()
H A DLegalizerHelper.cpp917 Register PtrReg = MI.getOperand(1).getReg(); in narrowScalar() local
924 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); in narrowScalar()
926 MIRBuilder.buildLoadInstr(MI.getOpcode(), TmpReg, PtrReg, MMO); in narrowScalar()
2721 Register PtrReg = MI.getOperand(1).getReg(); in lowerLoad() local
2754 LLT PtrTy = MRI.getType(PtrReg); in lowerLoad()
2760 TargetOpcode::G_ZEXTLOAD, LargeLdReg, PtrReg, *LargeMMO); in lowerLoad()
2766 MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0)); in lowerLoad()
2778 MIRBuilder.buildLoad(DstReg, PtrReg, MMO); in lowerLoad()
2786 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); in lowerLoad()
2817 Register PtrReg = MI.getOperand(1).getReg(); in lowerStore() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp11216 Register PtrReg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary() local
11278 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) in EmitPartwordAtomicBinary()
11283 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) in EmitPartwordAtomicBinary()
11304 .addReg(PtrReg); in EmitPartwordAtomicBinary()
11348 .addReg(PtrReg); in EmitPartwordAtomicBinary()
12222 Register PtrReg = RegInfo.createVirtualRegister(RC); in EmitInstrWithCustomInserter() local
12292 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) in EmitInstrWithCustomInserter()
12297 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) in EmitInstrWithCustomInserter()
12329 .addReg(PtrReg); in EmitInstrWithCustomInserter()
12353 .addReg(PtrReg); in EmitInstrWithCustomInserter()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp2621 const Register PtrReg = I.getOperand(1).getReg(); in select() local
2622 const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI); in select()
2626 assert(MRI.getType(PtrReg).isPointer() && in select()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp4673 unsigned PtrReg = Use64BitPtr ? X86::RAX : X86::EAX; in Select() local
4674 SDValue Chain = CurDAG->getCopyToReg(Node->getOperand(0), dl, PtrReg, in Select()