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Searched refs:PrevReg (Results 1 – 9 of 9) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSILowerI1Copies.cpp88 unsigned DstReg, unsigned PrevReg, unsigned CurReg);
810 unsigned PrevReg, unsigned CurReg) { in buildMergeLaneMasks() argument
812 bool PrevConstant = isConstantLaneMask(PrevReg, PrevVal); in buildMergeLaneMasks()
833 PrevMaskedReg = PrevReg; in buildMergeLaneMasks()
837 .addReg(PrevReg) in buildMergeLaneMasks()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DRegAllocFast.cpp850 MCPhysReg PrevReg = LRI->PhysReg; in defineLiveThroughVirtReg() local
851 if (PrevReg != 0 && isRegUsedInInstr(PrevReg, true)) { in defineLiveThroughVirtReg()
852 LLVM_DEBUG(dbgs() << "Need new assignment for " << printReg(PrevReg, TRI) in defineLiveThroughVirtReg()
854 freePhysReg(PrevReg); in defineLiveThroughVirtReg()
860 << printReg(PrevReg, TRI) << '\n'); in defineLiveThroughVirtReg()
862 TII->get(TargetOpcode::COPY), PrevReg) in defineLiveThroughVirtReg()
H A DModuloSchedule.cpp561 unsigned PrevReg = 0; in generateExistingPhis() local
563 PrevReg = VRMap[PrevStage - np][LoopVal]; in generateExistingPhis()
565 NewReg, PrevReg); in generateExistingPhis()
1143 unsigned PrevReg) { in rewriteScheduledInstr() argument
1171 if (PrevReg && InProlog) in rewriteScheduledInstr()
1172 ReplaceReg = PrevReg; in rewriteScheduledInstr()
1173 else if (PrevReg && !isLoopCarried(*Phi) && in rewriteScheduledInstr()
1175 ReplaceReg = PrevReg; in rewriteScheduledInstr()
H A DRegAllocGreedy.cpp471 Register canReassign(LiveInterval &VirtReg, Register PrevReg) const;
853 Register RAGreedy::canReassign(LiveInterval &VirtReg, Register PrevReg) const { in canReassign()
858 if ((*I).id() == PrevReg.id()) in canReassign()
874 << printReg(PrevReg, TRI) << " to " in canReassign()
H A DMachinePipeliner.cpp2186 unsigned PrevReg = getLoopPhiReg(*Phi, MI->getParent()); in canUseLastOffsetValue() local
2187 if (!PrevReg) in canUseLastOffsetValue()
2191 MachineInstr *PrevDef = MRI.getVRegDef(PrevReg); in canUseLastOffsetValue()
2216 NewBase = PrevReg; in canUseLastOffsetValue()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DModuloSchedule.h229 unsigned NewReg, unsigned PrevReg = 0);
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp588 MCOperand PrevReg = MCOperand::createReg(Sparc::G0); in expandSET() local
601 PrevReg = MCRegOp; in expandSET()
624 TmpInst.addOperand(PrevReg); in expandSET()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp1422 int PrevReg = *RegList.List->begin(); in isRegList16() local
1425 if ( Reg != PrevReg + 1) in isRegList16()
1427 PrevReg = Reg; in isRegList16()
6793 unsigned PrevReg = Mips::NoRegister; in parseRegisterList() local
6812 unsigned TmpReg = PrevReg + 1; in parseRegisterList()
6821 PrevReg = TmpReg; in parseRegisterList()
6828 if ((PrevReg == Mips::NoRegister) && in parseRegisterList()
6841 } else if ((PrevReg != Mips::NoRegister) && (RegNo != PrevReg + 1) && in parseRegisterList()
6865 PrevReg = RegNo; in parseRegisterList()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp3512 int64_t PrevReg = FirstReg; in tryParseVectorList() local
3530 unsigned Space = (PrevReg < Reg) ? (Reg - PrevReg) : (Reg + 32 - PrevReg); in tryParseVectorList()
3556 (getContext().getRegisterInfo()->getEncodingValue(PrevReg) + 1) % 32) { in tryParseVectorList()
3561 PrevReg = Reg; in tryParseVectorList()