| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| H A D | PPCPredicates.cpp | 18 PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) { in InvertPredicate()
20 case PPC::PRED_EQ: return PPC::PRED_NE; in InvertPredicate()
21 case PPC::PRED_NE: return PPC::PRED_EQ; in InvertPredicate()
22 case PPC::PRED_LT: return PPC::PRED_GE; in InvertPredicate()
23 case PPC::PRED_GE: return PPC::PRED_LT; in InvertPredicate()
24 case PPC::PRED_GT: return PPC::PRED_LE; in InvertPredicate()
25 case PPC::PRED_LE: return PPC::PRED_GT; in InvertPredicate()
26 case PPC::PRED_NU: return PPC::PRED_UN; in InvertPredicate()
27 case PPC::PRED_UN: return PPC::PRED_NU; in InvertPredicate()
28 case PPC::PRED_EQ_MINUS: return PPC::PRED_NE_PLUS; in InvertPredicate()
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| H A D | PPCMCTargetDesc.h | 17 #undef PPC
110 #undef PPC
161 static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC::R); \
162 static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC::X); \
163 static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC::F); \
164 static const MCPhysReg VSRpRegs[32] = PPC_REGS0_31(PPC::VSRp); \
165 static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC::S); \
166 static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC::VF); \
167 static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC::V); \
169 PPC_REGS_NO0_31(PPC::ZERO, PPC::R); \
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| H A D | PPCInstPrinter.cpp | 63 (MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) && in printInst()
96 if (MI->getOpcode() == PPC::PLDpc) { in printInst()
114 if (MI->getOpcode() == PPC::RLWINM) { in printInst()
137 if (MI->getOpcode() == PPC::RLDICR || in printInst()
138 MI->getOpcode() == PPC::RLDICR_32) { in printInst()
161 if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) { in printInst()
164 if (MI->getOpcode() == PPC::DCBTST) in printInst()
170 bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE]; in printInst()
185 if (MI->getOpcode() == PPC::DCBF) { in printInst()
222 switch ((PPC::Predicate)Code) { in printPredicateOperand()
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| H A D | PPCAsmBackend.cpp | 35 case PPC::fixup_ppc_nofixup: in adjustFixupValue()
37 case PPC::fixup_ppc_brcond14: in adjustFixupValue()
38 case PPC::fixup_ppc_brcond14abs: in adjustFixupValue()
40 case PPC::fixup_ppc_br24: in adjustFixupValue()
41 case PPC::fixup_ppc_br24abs: in adjustFixupValue()
42 case PPC::fixup_ppc_br24_notoc: in adjustFixupValue()
44 case PPC::fixup_ppc_half16: in adjustFixupValue()
46 case PPC::fixup_ppc_half16ds: in adjustFixupValue()
48 case PPC::fixup_ppc_pcrel34: in adjustFixupValue()
49 case PPC::fixup_ppc_imm34: in adjustFixupValue()
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| H A D | PPCMCCodeEmitter.cpp | 52 ((MI.getOpcode() == PPC::BL8_NOTOC || in getDirectBrEncoding()
53 MI.getOpcode() == PPC::BL8_NOTOC_TLS) in getDirectBrEncoding()
54 ? (MCFixupKind)PPC::fixup_ppc_br24_notoc in getDirectBrEncoding()
55 : (MCFixupKind)PPC::fixup_ppc_br24))); in getDirectBrEncoding()
67 (MCFixupKind)PPC::fixup_ppc_brcond14)); in getCondBrEncoding()
80 (MCFixupKind)PPC::fixup_ppc_br24abs)); in getAbsDirectBrEncoding()
93 (MCFixupKind)PPC::fixup_ppc_brcond14abs)); in getAbsCondBrEncoding()
115 (MCFixupKind)PPC::fixup_ppc_half16)); in getImm16Encoding()
138 (MCFixupKind)PPC::fixup_ppc_imm34); in getImm34EncodingNoPCRel()
146 (MCFixupKind)PPC::fixup_ppc_pcrel34); in getImm34EncodingPCRel()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 91 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP, in PPCInstrInfo()
93 STI.isPPC64() ? PPC::BLR8 : PPC::BLR), in PPCInstrInfo()
103 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 || in CreateTargetHazardRecognizer()
104 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) { in CreateTargetHazardRecognizer()
122 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8) in CreateTargetPostRAHazardRecognizer()
126 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 && in CreateTargetPostRAHazardRecognizer()
127 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) { in CreateTargetPostRAHazardRecognizer()
183 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) || in getOperandLatency()
184 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass); in getOperandLatency()
186 IsRegCR = PPC::CRRCRegClass.contains(Reg) || in getOperandLatency()
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| H A D | PPCRegisterInfo.cpp | 96 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR, in PPCRegisterInfo()
100 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; in PPCRegisterInfo()
101 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; in PPCRegisterInfo()
102 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; in PPCRegisterInfo()
103 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; in PPCRegisterInfo()
104 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; in PPCRegisterInfo()
105 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; in PPCRegisterInfo()
106 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; in PPCRegisterInfo()
107 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; in PPCRegisterInfo()
108 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32; in PPCRegisterInfo()
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| H A D | PPCInstrInfo.h | 134 #define NoInstr PPC::INSTRUCTION_LIST_END
137 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
138 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX, \
139 PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, PPC::EVLDD \
144 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
145 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
146 PPC::DFLOADf32, PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, NoInstr \
151 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
152 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
153 PPC::DFLOADf32, PPC::SPILLTOVSR_LD, PPC::LXVP, PPC::RESTORE_ACC, \
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| H A D | PPCMIPeephole.cpp | 132 assert((MF.getRegInfo().use_empty(PPC::X2) || in runOnMachineFunction()
172 if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec || in getKnownLeadingZeroCount()
173 Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec) in getKnownLeadingZeroCount()
176 if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDIC_rec) && in getKnownLeadingZeroCount()
180 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec || in getKnownLeadingZeroCount()
181 Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec || in getKnownLeadingZeroCount()
182 Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) && in getKnownLeadingZeroCount()
186 if (Opcode == PPC::ANDI_rec) { in getKnownLeadingZeroCount()
191 if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZW_rec || in getKnownLeadingZeroCount()
192 Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZW_rec || in getKnownLeadingZeroCount()
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| H A D | PPCVSXSwapRemoval.cpp | 168 return (isRegInClass(Reg, &PPC::VSRCRegClass) || in isVecReg()
169 isRegInClass(Reg, &PPC::VRRCRegClass)); in isVecReg()
174 return (isRegInClass(Reg, &PPC::VSFRCRegClass) || in isScalarVecReg()
175 isRegInClass(Reg, &PPC::VSSRCRegClass)); in isScalarVecReg()
288 case PPC::XXPERMDI: { in gatherVectorInstructions()
337 case PPC::LVX: in gatherVectorInstructions()
344 case PPC::LXVD2X: in gatherVectorInstructions()
345 case PPC::LXVW4X: in gatherVectorInstructions()
351 case PPC::LXSDX: in gatherVectorInstructions()
352 case PPC::LXSSPX: in gatherVectorInstructions()
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| H A D | PPCFastISel.cpp | 145 return RC->getID() == PPC::VSFRCRegClassID; in isVSFRCRegClass()
148 return RC->getID() == PPC::VSSRCRegClassID; in isVSSRCRegClass()
160 const PPC::Predicate Pred);
163 unsigned FP64LoadOpc = PPC::LFD);
201 static Optional<PPC::Predicate> getComparePred(CmpInst::Predicate Pred) { in getComparePred()
229 return Optional<PPC::Predicate>(); in getComparePred()
233 return PPC::PRED_EQ; in getComparePred()
238 return PPC::PRED_GT; in getComparePred()
243 return PPC::PRED_GE; in getComparePred()
248 return PPC::PRED_LT; in getComparePred()
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| H A D | PPCRegisterInfo.h | 28 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || in getCRFromCRBit()
29 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) in getCRFromCRBit()
30 Reg = PPC::CR0; in getCRFromCRBit()
31 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || in getCRFromCRBit()
32 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) in getCRFromCRBit()
33 Reg = PPC::CR1; in getCRFromCRBit()
34 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || in getCRFromCRBit()
35 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) in getCRFromCRBit()
36 Reg = PPC::CR2; in getCRFromCRBit()
37 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || in getCRFromCRBit()
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| H A D | PPCFrameLowering.cpp | 97 {PPC::F31, -8}, \ in getCalleeSavedSpillSlots()
98 {PPC::F30, -16}, \ in getCalleeSavedSpillSlots()
99 {PPC::F29, -24}, \ in getCalleeSavedSpillSlots()
100 {PPC::F28, -32}, \ in getCalleeSavedSpillSlots()
101 {PPC::F27, -40}, \ in getCalleeSavedSpillSlots()
102 {PPC::F26, -48}, \ in getCalleeSavedSpillSlots()
103 {PPC::F25, -56}, \ in getCalleeSavedSpillSlots()
104 {PPC::F24, -64}, \ in getCalleeSavedSpillSlots()
105 {PPC::F23, -72}, \ in getCalleeSavedSpillSlots()
106 {PPC::F22, -80}, \ in getCalleeSavedSpillSlots()
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| H A D | PPCCallingConv.cpp | 37 PPC::R3, PPC::R4, PPC::R5, PPC::R6, in CC_PPC32_SVR4_Custom_AlignArgRegs()
38 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_AlignArgRegs()
62 PPC::R3, PPC::R4, PPC::R5, PPC::R6, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
63 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
87 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
88 PPC::F8 in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
97 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
114 static const MCPhysReg HiRegList[] = { PPC::R3, PPC::R5, PPC::R7, PPC::R9 }; in CC_PPC32_SPE_CustomSplitFP64()
115 static const MCPhysReg LoRegList[] = { PPC::R4, PPC::R6, PPC::R8, PPC::R10 }; in CC_PPC32_SPE_CustomSplitFP64()
143 static const MCPhysReg HiRegList[] = { PPC::R3 }; in CC_PPC32_SPE_RetF64()
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| H A D | PPCTLSDynamicCall.cpp | 61 if (MI.getOpcode() != PPC::ADDItlsgdLADDR && in processBlock()
62 MI.getOpcode() != PPC::ADDItlsldLADDR && in processBlock()
63 MI.getOpcode() != PPC::ADDItlsgdLADDR32 && in processBlock()
64 MI.getOpcode() != PPC::ADDItlsldLADDR32 && in processBlock()
65 MI.getOpcode() != PPC::TLSGDAIX && in processBlock()
66 MI.getOpcode() != PPC::TLSGDAIX8 && !IsPCREL) { in processBlock()
71 if (MI.getOpcode() == PPC::ADJCALLSTACKDOWN) in processBlock()
73 else if (MI.getOpcode() == PPC::ADJCALLSTACKUP) in processBlock()
83 Register InReg = PPC::NoRegister; in processBlock()
84 Register GPR3 = Is64Bit ? PPC::X3 : PPC::R3; in processBlock()
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| H A D | PPCISelDAGToDAG.cpp | 246 Align(4)) == PPC::AM_DSForm; in SelectDSForm()
254 Align(16)) == PPC::AM_DQForm; in SelectDQForm()
262 None) == PPC::AM_DForm; in SelectDForm()
269 None) == PPC::AM_XForm; in SelectXForm()
277 PPC::AM_XForm; in SelectForceXForm()
442 GlobalBaseReg = PPC::R30; in getGlobalBaseReg()
445 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MoveGOTtoLR)); in getGlobalBaseReg()
446 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); in getGlobalBaseReg()
449 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR)); in getGlobalBaseReg()
450 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); in getGlobalBaseReg()
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| H A D | PPCPreEmitPeephole.cpp | 55 case PPC::LBZ: in hasPCRelativeForm()
56 case PPC::LBZ8: in hasPCRelativeForm()
57 case PPC::LHA: in hasPCRelativeForm()
58 case PPC::LHA8: in hasPCRelativeForm()
59 case PPC::LHZ: in hasPCRelativeForm()
60 case PPC::LHZ8: in hasPCRelativeForm()
61 case PPC::LWZ: in hasPCRelativeForm()
62 case PPC::LWZ8: in hasPCRelativeForm()
63 case PPC::STB: in hasPCRelativeForm()
64 case PPC::STB8: in hasPCRelativeForm()
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| H A D | PPCAsmPrinter.cpp | 326 Reg = PPC::VSX32 + (Reg - PPC::V0); in PrintAsmOperand()
328 Reg = PPC::VSX32 + (Reg - PPC::VF0); in PrintAsmOperand()
414 MII->getOpcode() == PPC::DBG_VALUE || in LowerSTACKMAP()
424 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::NOP)); in LowerSTACKMAP()
448 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::LI8) in LowerPATCHPOINT()
452 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::RLDIC) in LowerPATCHPOINT()
457 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::ORIS8) in LowerPATCHPOINT()
462 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::ORI8) in LowerPATCHPOINT()
469 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::STD) in LowerPATCHPOINT()
470 .addReg(PPC::X2) in LowerPATCHPOINT()
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| H A D | PPCHazardRecognizers.cpp | 66 if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR) in isBCTRAfterSet()
81 namespace llvm { namespace PPC { extern int getNonRecordFormOpcode(uint16_t); } } namespace
95 case PPC::Sched::IIC_IntDivW: in mustComeFirst()
96 case PPC::Sched::IIC_IntDivD: in mustComeFirst()
97 case PPC::Sched::IIC_LdStLoadUpd: in mustComeFirst()
98 case PPC::Sched::IIC_LdStLDU: in mustComeFirst()
99 case PPC::Sched::IIC_LdStLFDU: in mustComeFirst()
100 case PPC::Sched::IIC_LdStLFDUX: in mustComeFirst()
101 case PPC::Sched::IIC_LdStLHA: in mustComeFirst()
102 case PPC::Sched::IIC_LdStLHAU: in mustComeFirst()
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| H A D | PPCReduceCRLogicals.cpp | 158 OrigBROpcode == PPC::BC in splitMBB()
159 ? PPC::BCn in splitMBB()
160 : OrigBROpcode == PPC::BCn in splitMBB()
161 ? PPC::BC in splitMBB()
162 : OrigBROpcode == PPC::BCLR ? PPC::BCLRn : PPC::BCLR; in splitMBB()
225 TII->get(PPC::B)) in splitMBB()
274 if (BROp == PPC::BC || BROp == PPC::BCLR) { in computeBranchTargetAndInversion()
279 case PPC::CROR: in computeBranchTargetAndInversion()
284 case PPC::CRAND: in computeBranchTargetAndInversion()
289 case PPC::CRNAND: in computeBranchTargetAndInversion()
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| H A D | PPCBranchSelector.cpp | 112 !Fn.getRegInfo().use_empty(PPC::X2)) in GetInitialOffset()
335 if (I->getOpcode() == PPC::BCC && !I->getOperand(2).isImm()) in runOnMachineFunction()
337 else if ((I->getOpcode() == PPC::BC || I->getOpcode() == PPC::BCn) && in runOnMachineFunction()
340 else if ((I->getOpcode() == PPC::BDNZ8 || I->getOpcode() == PPC::BDNZ || in runOnMachineFunction()
341 I->getOpcode() == PPC::BDZ8 || I->getOpcode() == PPC::BDZ) && in runOnMachineFunction()
364 if (I->getOpcode() == PPC::BCC) { in runOnMachineFunction()
369 PPC::Predicate Pred = (PPC::Predicate)I->getOperand(0).getImm(); in runOnMachineFunction()
373 BuildMI(MBB, I, dl, TII->get(PPC::BCC)) in runOnMachineFunction()
374 .addImm(PPC::InvertPredicate(Pred)).addReg(CRReg).addImm(2); in runOnMachineFunction()
375 } else if (I->getOpcode() == PPC::BC) { in runOnMachineFunction()
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| H A D | PPCISelLowering.cpp | 149 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); in PPCTargetLowering()
152 addRegisterClass(MVT::f32, &PPC::GPRCRegClass); in PPCTargetLowering()
155 addRegisterClass(MVT::f64, &PPC::SPERCRegClass); in PPCTargetLowering()
157 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); in PPCTargetLowering()
158 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); in PPCTargetLowering()
277 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass); in PPCTargetLowering()
684 addRegisterClass(MVT::i64, &PPC::G8RCRegClass); in PPCTargetLowering()
881 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass); in PPCTargetLowering()
882 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass); in PPCTargetLowering()
883 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass); in PPCTargetLowering()
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| H A D | PPCCTRLoops.cpp | 87 if (MO.isDef() && (MO.getReg() == PPC::CTR || MO.getReg() == PPC::CTR8)) in clobbersCTR()
90 if (MO.clobbersPhysReg(PPC::CTR) || MO.clobbersPhysReg(PPC::CTR8)) in clobbersCTR()
119 if (Opc == PPC::MTCTRloop || Opc == PPC::MTCTR8loop) { in verifyCTRBranch()
179 if (Opc == PPC::BDNZ8 || Opc == PPC::BDNZ || in runOnMachineFunction()
180 Opc == PPC::BDZ8 || Opc == PPC::BDZ) in runOnMachineFunction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/AsmParser/ |
| H A D | PPCAsmParser.cpp | 749 case PPC::DCBTx: in ProcessInstruction()
750 case PPC::DCBTT: in ProcessInstruction()
751 case PPC::DCBTSTx: in ProcessInstruction()
752 case PPC::DCBTSTT: { in ProcessInstruction()
754 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ? in ProcessInstruction()
755 PPC::DCBT : PPC::DCBTST); in ProcessInstruction()
757 (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16)); in ProcessInstruction()
763 case PPC::DCBTCT: in ProcessInstruction()
764 case PPC::DCBTDS: { in ProcessInstruction()
766 TmpInst.setOpcode(PPC::DCBT); in ProcessInstruction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/PowerPC/ |
| H A D | Target.cpp | 46 return PPC::LI; in getLoadImmediateOpcode()
48 return PPC::LI8; in getLoadImmediateOpcode()
70 return TT.isArch64Bit() ? PPC::X13 : PPC::R13; in getScratchMemoryRegister()
85 setMemOp(IT, DispOpIdx, MCOperand::createReg(PPC::X1)); in fillMemoryOperands()
96 unsigned ScratchImmReg = PPC::X11; in setRegTo()
98 if (PPC::GPRCRegClass.contains(Reg)) in setRegTo()
100 if (PPC::G8RCRegClass.contains(Reg)) in setRegTo()
102 if (PPC::F4RCRegClass.contains(Reg)) in setRegTo()
104 MCInstBuilder(PPC::MTVSRD).addReg(Reg).addReg(ScratchImmReg)}; in setRegTo()
108 if (PPC::VRRCRegClass.contains(Reg)) in setRegTo()
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