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Searched refs:PLL4 (Results 1 – 6 of 6) sorted by relevance

/netbsd-src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
H A Dqcom,lcc-ipq806x.h11 #define PLL4 0 macro
H A Dqcom,lcc-mdm9615.h13 #define PLL4 0 macro
H A Dqcom,lcc-msm8960.h11 #define PLL4 0 macro
H A Dstm32mp1-clks.h188 #define PLL4 179 macro
/netbsd-src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
H A Dstm32mp157c-odyssey.dts35 assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */
/netbsd-src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/ti/
H A Dk3-am65-main.dtsi849 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via