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Searched refs:PIPE_C (Results 1 – 20 of 20) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/gvt/
H A Dhandlers.c645 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C))
648 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C))
651 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C))
759 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
782 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C))
1984 MMIO_D(PIPEDSL(PIPE_C), D_ALL); in init_generic_mmio_info()
1989 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
1994 MMIO_D(PIPESTAT(PIPE_C), D_ALL); in init_generic_mmio_info()
1999 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL); in init_generic_mmio_info()
2004 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL); in init_generic_mmio_info()
[all …]
H A Dreg.h78 (((p) == PIPE_C) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x5008C)) : \
86 (((reg) == 0x5008C || (reg) == 0x5009C) ? (PIPE_C) : \
H A Ddisplay.c57 pipe = PIPE_C; in get_edp_pipe()
402 [PIPE_C] = PIPE_C_VBLANK, in emulate_vblank_on_pipe()
406 if (pipe < PIPE_A || pipe > PIPE_C) in emulate_vblank_on_pipe()
H A Dcmd_parser.c1227 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE}, in gen8_decode_mi_display_flip()
1228 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE}, in gen8_decode_mi_display_flip()
1286 info->pipe = PIPE_C; in skl_decode_mi_display_flip()
1301 info->pipe = PIPE_C; in skl_decode_mi_display_flip()
H A Dinterrupt.c456 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_c, GEN8_DE_PIPE_ISR(PIPE_C));
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/
H A Di915_pci.c116 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
123 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
130 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
436 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
587 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
660 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
826 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
H A Dintel_device_info.c932 runtime->num_scalers[PIPE_C] = 1; in intel_device_info_runtime_init()
955 runtime->num_sprites[PIPE_C] = 1; in intel_device_info_runtime_init()
986 info->pipe_mask &= ~BIT(PIPE_C); in intel_device_info_runtime_init()
997 enabled_mask &= ~BIT(PIPE_C); in intel_device_info_runtime_init()
H A Dintel_pm.c496 case PIPE_C: in vlv_get_fifo_size()
1034 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) | in vlv_write_wm_values()
1035 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE)); in vlv_write_wm_values()
1037 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) | in vlv_write_wm_values()
1038 FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC)); in vlv_write_wm_values()
1041 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) | in vlv_write_wm_values()
1042 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) | in vlv_write_wm_values()
1043 FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) | in vlv_write_wm_values()
1930 wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1; in vlv_compute_pipe_wm()
2041 case PIPE_C: in vlv_atomic_update_fifo()
[all …]
H A Di915_irq.c1335 case PIPE_C: in i9xx_pipestat_irq_ack()
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/
H A Dintel_pipe_crc.c190 case PIPE_C: in vlv_pipe_crc_ctl_reg()
254 case PIPE_C: in vlv_undo_pipe_scramble_reset()
H A Dintel_display_power.c1504 pipe = PIPE_C; in chv_dpio_cmn_power_well_enable()
1565 assert_pll_disabled(dev_priv, PIPE_C); in chv_dpio_cmn_power_well_disable()
1585 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; in assert_chv_phy_powergate()
2861 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3062 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3144 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3204 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3373 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3694 .hsw.irq_pipe_mask = BIT(PIPE_C),
3839 .hsw.irq_pipe_mask = BIT(PIPE_C),
[all …]
H A Dintel_display.h109 PIPE_C, enumerator
128 TRANSCODER_C = PIPE_C,
H A Dicl_dsi.c770 case PIPE_C: in gen11_dsi_configure_transcoder()
1460 *pipe = PIPE_C; in gen11_dsi_get_hw_state()
H A Dintel_display_types.h1418 case PIPE_C: in vlv_pipe_to_channel()
H A Dintel_sprite.c2871 if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C) in skl_plane_has_planar()
2940 return pipe != PIPE_C; in skl_plane_has_ccs()
2942 return pipe != PIPE_C && in skl_plane_has_ccs()
H A Dvlv_dsi.c1015 if (WARN_ON(tmp > PIPE_C)) in intel_dsi_get_hw_state()
H A Dintel_ddi.c1882 case PIPE_C: in intel_ddi_transcoder_func_reg_val_get()
2110 *pipe_mask = BIT(PIPE_C); in intel_ddi_get_encoder_pipes()
H A Dintel_display.c5679 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); in cpt_set_fdi_bc_bifurcation()
5705 case PIPE_C: in ivb_update_fdi_bc_bifurcation()
7675 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C); in ilk_check_fdi_lanes()
7687 case PIPE_C: in ilk_check_fdi_lanes()
8655 (pipe == PIPE_B || pipe == PIPE_C)) in intel_set_pipe_timings()
10765 trans_pipe = PIPE_C; in hsw_get_transcoder_state()
11524 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C && in i9xx_check_cursor()
H A Dintel_hdmi.c3301 intel_encoder->pipe_mask = BIT(PIPE_C); in intel_hdmi_init()
H A Dintel_dp.c7659 intel_encoder->pipe_mask = BIT(PIPE_C); in intel_dp_init()