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Searched refs:PIPE_B (Results 1 – 25 of 27) sorted by relevance

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/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/gvt/
H A Dhandlers.c1983 MMIO_D(PIPEDSL(PIPE_B), D_ALL); in init_generic_mmio_info()
1988 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
1993 MMIO_D(PIPESTAT(PIPE_B), D_ALL); in init_generic_mmio_info()
1998 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); in init_generic_mmio_info()
2003 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); in init_generic_mmio_info()
2008 MMIO_D(CURCNTR(PIPE_B), D_ALL); in init_generic_mmio_info()
2012 MMIO_D(CURPOS(PIPE_B), D_ALL); in init_generic_mmio_info()
2016 MMIO_D(CURBASE(PIPE_B), D_ALL); in init_generic_mmio_info()
2020 MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL); in init_generic_mmio_info()
2043 MMIO_D(DSPCNTR(PIPE_B), D_ALL); in init_generic_mmio_info()
[all …]
H A Dreg.h76 (((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \
85 (((reg) == 0x50088 || (reg) == 0x50098) ? (PIPE_B) : \
H A Ddisplay.c54 pipe = PIPE_B; in get_edp_pipe()
401 [PIPE_B] = PIPE_B_VBLANK, in emulate_vblank_on_pipe()
H A Dcmd_parser.c1224 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE}, in gen8_decode_mi_display_flip()
1226 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE}, in gen8_decode_mi_display_flip()
1282 info->pipe = PIPE_B; in skl_decode_mi_display_flip()
1296 info->pipe = PIPE_B; in skl_decode_mi_display_flip()
H A Dinterrupt.c455 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_b, GEN8_DE_PIPE_ISR(PIPE_B));
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/
H A Di915_pci.c109 [PIPE_B] = CURSOR_B_OFFSET, \
115 [PIPE_B] = CURSOR_B_OFFSET, \
122 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
129 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
166 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
224 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
309 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
360 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
387 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
436 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
[all …]
H A Di915_reg.h8136 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8139 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8142 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8145 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8164 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8167 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8170 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8173 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8189 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8192 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
[all …]
H A Dintel_pm.c490 case PIPE_B: in vlv_get_fifo_size()
969 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | in g4x_write_wm_values()
970 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | in g4x_write_wm_values()
976 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) | in g4x_write_wm_values()
1019 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | in vlv_write_wm_values()
1020 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | in vlv_write_wm_values()
1031 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) | in vlv_write_wm_values()
1032 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC)); in vlv_write_wm_values()
1044 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) | in vlv_write_wm_values()
1045 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) | in vlv_write_wm_values()
[all …]
H A Dintel_device_info.c931 runtime->num_scalers[PIPE_B] = 2; in intel_device_info_runtime_init()
954 runtime->num_sprites[PIPE_B] = 2; in intel_device_info_runtime_init()
995 enabled_mask &= ~BIT(PIPE_B); in intel_device_info_runtime_init()
H A Di915_irq.c524 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); in i915_enable_asle_pipestat()
1332 case PIPE_B: in i9xx_pipestat_irq_ack()
1767 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); in ibx_irq_handler()
3525 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
3699 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
3817 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/
H A Dintel_dpio_phy.c802 if (ch == DPIO_CH0 && pipe == PIPE_B) in chv_phy_pre_pll_enable()
814 if (pipe != PIPE_B) { in chv_phy_pre_pll_enable()
835 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
844 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
857 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
967 if (pipe != PIPE_B) { in chv_phy_post_pll_disable()
H A Dintel_display_power.c1122 if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1123 i830_enable_pipe(dev_priv, PIPE_B); in i830_pipes_power_well_enable()
1129 i830_disable_pipe(dev_priv, PIPE_B); in i830_pipes_power_well_disable()
1137 I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in i830_pipes_power_well_enabled()
1438 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
1562 assert_pll_disabled(dev_priv, PIPE_B); in chv_dpio_cmn_power_well_disable()
2861 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3062 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3144 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3204 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
[all …]
H A Dintel_pipe_crc.c187 case PIPE_B: in vlv_pipe_crc_ctl_reg()
251 case PIPE_B: in vlv_undo_pipe_scramble_reset()
H A Dintel_display.h108 PIPE_B, enumerator
127 TRANSCODER_B = PIPE_B,
H A Dvlv_dsi.c996 enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in intel_dsi_get_hw_state()
1020 *pipe = port == PORT_A ? PIPE_A : PIPE_B; in intel_dsi_get_hw_state()
1879 intel_encoder->pipe_mask = BIT(PIPE_B); in vlv_dsi_init()
H A Dintel_dp.c835 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); in vlv_find_free_pps()
965 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe()
3657 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
4263 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { in intel_dp_link_down()
7425 if (pipe != PIPE_A && pipe != PIPE_B) in intel_edp_init_connector()
7428 if (pipe != PIPE_A && pipe != PIPE_B) in intel_edp_init_connector()
7661 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in intel_dp_init()
H A Dicl_dsi.c767 case PIPE_B: in gen11_dsi_configure_transcoder()
1457 *pipe = PIPE_B; in gen11_dsi_get_hw_state()
H A Dintel_display_types.h1420 case PIPE_B: in vlv_pipe_to_channel()
H A Dintel_lvds.c908 intel_encoder->pipe_mask = BIT(PIPE_B); in intel_lvds_init()
H A Dintel_sprite.c1048 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) in vlv_update_plane()
3087 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_sprite_plane_create()
3136 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_sprite_plane_create()
H A Dintel_display.c1350 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, in assert_pch_dp_disabled()
1368 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, in assert_pch_hdmi_disabled()
1483 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
1491 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); in chv_enable_pll()
5678 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); in cpt_set_fdi_bc_bifurcation()
5698 case PIPE_B: in ivb_update_fdi_bc_bifurcation()
7327 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in valleyview_crtc_enable()
7671 case PIPE_B: in ilk_check_fdi_lanes()
7694 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); in ilk_check_fdi_lanes()
8245 if (pipe == PIPE_B) in vlv_prepare_pll()
[all …]
H A Dintel_panel.c581 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in _vlv_get_backlight()
1759 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_setup_backlight()
H A Dintel_hdmi.c2033 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { in intel_disable_hdmi()
3303 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in intel_hdmi_init()
/netbsd-src/sys/external/bsd/drm/dist/shared-core/
H A Di915_suspend.c308 i915_save_palette(dev, PIPE_B); in i915_save_state()
465 i915_restore_palette(dev, PIPE_B); in i915_restore_state()
H A Di915_drv.h46 PIPE_B, enumerator

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