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Searched refs:PIPE_A (Results 1 – 25 of 28) sorted by relevance

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/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/gvt/
H A Dhandlers.c1982 MMIO_D(PIPEDSL(PIPE_A), D_ALL); in init_generic_mmio_info()
1987 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
1992 MMIO_D(PIPESTAT(PIPE_A), D_ALL); in init_generic_mmio_info()
1997 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); in init_generic_mmio_info()
2002 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); in init_generic_mmio_info()
2007 MMIO_D(CURCNTR(PIPE_A), D_ALL); in init_generic_mmio_info()
2011 MMIO_D(CURPOS(PIPE_A), D_ALL); in init_generic_mmio_info()
2015 MMIO_D(CURBASE(PIPE_A), D_ALL); in init_generic_mmio_info()
2019 MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL); in init_generic_mmio_info()
2032 MMIO_D(DSPCNTR(PIPE_A), D_ALL); in init_generic_mmio_info()
[all …]
H A Ddisplay.c51 pipe = PIPE_A; in get_edp_pipe()
79 if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES)) in pipe_is_enabled()
310 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; in emulate_monitor_status_change()
400 [PIPE_A] = PIPE_A_VBLANK, in emulate_vblank_on_pipe()
406 if (pipe < PIPE_A || pipe > PIPE_C) in emulate_vblank_on_pipe()
H A Dreg.h74 (((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \
84 (((reg) == 0x50080 || (reg) == 0x50090) ? (PIPE_A) : \
H A Dcmd_parser.c1223 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE}, in gen8_decode_mi_display_flip()
1225 [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE}, in gen8_decode_mi_display_flip()
1278 info->pipe = PIPE_A; in skl_decode_mi_display_flip()
1291 info->pipe = PIPE_A; in skl_decode_mi_display_flip()
H A Dinterrupt.c454 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_a, GEN8_DE_PIPE_ISR(PIPE_A));
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/
H A Di915_pci.c103 [PIPE_A] = CURSOR_A_OFFSET, \
108 [PIPE_A] = CURSOR_A_OFFSET, \
114 [PIPE_A] = CURSOR_A_OFFSET, \
121 [PIPE_A] = CURSOR_A_OFFSET, \
128 [PIPE_A] = CURSOR_A_OFFSET, \
166 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
185 .pipe_mask = BIT(PIPE_A), \
224 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
309 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
360 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
[all …]
H A Dintel_pm.c484 case PIPE_A: in vlv_get_fifo_size()
971 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); in g4x_write_wm_values()
977 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in g4x_write_wm_values()
978 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); in g4x_write_wm_values()
1021 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); in vlv_write_wm_values()
1023 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) | in vlv_write_wm_values()
1024 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in vlv_write_wm_values()
1025 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); in vlv_write_wm_values()
1047 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) | in vlv_write_wm_values()
1048 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) | in vlv_write_wm_values()
[all …]
H A Dintel_device_info.c930 runtime->num_scalers[PIPE_A] = 2; in intel_device_info_runtime_init()
953 runtime->num_sprites[PIPE_A] = 2; in intel_device_info_runtime_init()
993 enabled_mask &= ~BIT(PIPE_A); in intel_device_info_runtime_init()
H A Di915_irq.c526 i915_enable_pipestat(dev_priv, PIPE_A, in i915_enable_asle_pipestat()
1329 case PIPE_A: in i9xx_pipestat_irq_ack()
1764 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); in ibx_irq_handler()
2737 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in vlv_display_irq_postinstall()
3524 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
3698 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
3815 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in i965_irq_postinstall()
3816 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
/netbsd-src/sys/external/bsd/drm/dist/shared-core/
H A Di915_suspend.c39 if (pipe == PIPE_A) in i915_pipe_enabled()
48 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B); in i915_save_palette()
55 if (pipe == PIPE_A) in i915_save_palette()
67 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B); in i915_restore_palette()
74 if (pipe == PIPE_A) in i915_restore_palette()
280 i915_save_palette(dev, PIPE_A); in i915_save_state()
423 i915_restore_palette(dev, PIPE_A); in i915_restore_state()
H A Di915_drv.h45 PIPE_A = 0, enumerator
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/
H A Dintel_ddi.c1132 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | in hsw_fdi_link_train()
1140 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
1141 POSTING_READ(FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
1146 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
1176 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); in hsw_fdi_link_train()
1180 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
1181 POSTING_READ(FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
1187 temp = I915_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
1189 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); in hsw_fdi_link_train()
1190 POSTING_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
[all …]
H A Dintel_crt.c240 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in hsw_disable_crt()
268 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in hsw_post_disable_crt()
279 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in hsw_pre_pll_enable_crt()
314 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in hsw_enable_crt()
1017 crt->base.pipe_mask = BIT(PIPE_A); in intel_crt_init()
1082 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; in intel_crt_init()
H A Dintel_pipe_crc.c184 case PIPE_A: in vlv_pipe_crc_ctl_reg()
248 case PIPE_A: in vlv_undo_pipe_scramble_reset()
321 pipe_config->hw.active && crtc->pipe == PIPE_A && in intel_crtc_crc_setup_workarounds()
H A Dintel_fifo_underrun.c138 u32 bit = (pipe == PIPE_A) ? in ilk_set_fifo_underrun_reporting()
204 u32 bit = (pch_transcoder == PIPE_A) ? in ibx_set_fifo_underrun_reporting()
H A Dintel_vdsc.c358 (pipe != PIPE_A || in intel_dsc_source_support()
382 WARN_ON(crtc->pipe == PIPE_A); in is_pipe_dsc()
492 if (INTEL_GEN(i915) >= 12 && pipe == PIPE_A) in intel_dsc_power_domain()
H A Dintel_display_power.c1120 if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1121 i830_enable_pipe(dev_priv, PIPE_A); in i830_pipes_power_well_enable()
1130 i830_disable_pipe(dev_priv, PIPE_A); in i830_pipes_power_well_disable()
1136 return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE && in i830_pipes_power_well_enabled()
1277 if (pipe != PIPE_A) in vlv_display_power_well_init()
1501 pipe = PIPE_A; in chv_dpio_cmn_power_well_enable()
1561 assert_pll_disabled(dev_priv, PIPE_A); in chv_dpio_cmn_power_well_disable()
1585 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; in assert_chv_phy_powergate()
1708 enum pipe pipe = PIPE_A; in chv_pipe_power_well_enabled()
1738 enum pipe pipe = PIPE_A; in chv_set_pipe_power_well()
[all …]
H A Dintel_dp.c835 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); in vlv_find_free_pps()
889 pipe = PIPE_A; in vlv_power_sequencer_pipe()
965 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe()
3255 *pipe = PIPE_A; in cpt_dp_port_selected()
3657 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
4268 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_dp_link_down()
4269 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_dp_link_down()
4273 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) | in intel_dp_link_down()
4282 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); in intel_dp_link_down()
4283 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_dp_link_down()
[all …]
H A Dintel_display.h107 PIPE_A = 0, enumerator
126 TRANSCODER_A = PIPE_A,
H A Dintel_display.c1475 if (pipe != PIPE_A) { in chv_enable_pll()
1578 if (pipe != PIPE_A) in vlv_disable_pll()
1595 if (pipe != PIPE_A) in chv_disable_pll()
1716 assert_fdi_rx_enabled(dev_priv, PIPE_A); in lpt_enable_pch_transcoder()
1718 val = I915_READ(TRANS_CHICKEN2(PIPE_A)); in lpt_enable_pch_transcoder()
1724 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); in lpt_enable_pch_transcoder()
1784 val = I915_READ(TRANS_CHICKEN2(PIPE_A)); in lpt_disable_pch_transcoder()
1786 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); in lpt_disable_pch_transcoder()
1794 return PIPE_A; in intel_crtc_pch_transcoder()
2720 crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A); in intel_plane_fb_max_stride()
[all …]
H A Dintel_hdmi.c2038 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_hdmi()
2039 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_hdmi()
2042 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); in intel_disable_hdmi()
2056 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); in intel_disable_hdmi()
2057 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_hdmi()
2058 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_hdmi()
3303 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in intel_hdmi_init()
H A Dintel_sdvo.c1757 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_sdvo()
1758 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_sdvo()
1761 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); in intel_disable_sdvo()
1767 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); in intel_disable_sdvo()
1768 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_sdvo()
1769 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_sdvo()
H A Dvlv_dsi.c1020 *pipe = port == PORT_A ? PIPE_A : PIPE_B; in intel_dsi_get_hw_state()
1877 intel_encoder->pipe_mask = BIT(PIPE_A); in vlv_dsi_init()
H A Dicl_dsi.c764 case PIPE_A: in gen11_dsi_configure_transcoder()
1454 *pipe = PIPE_A; in gen11_dsi_get_hw_state()
H A Dintel_display_types.h1417 case PIPE_A: in vlv_pipe_to_channel()

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