Searched refs:PFALSE (Results 1 – 9 of 9) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.h | 71 PFALSE, enumerator
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| H A D | HexagonISelLowering.cpp | 1894 case HexagonISD::PFALSE: return "HexagonISD::PFALSE"; in getTargetNodeName() 2751 return DAG.getNode(HexagonISD::PFALSE, dl, VecTy); in LowerBUILD_VECTOR() 3250 case HexagonISD::PFALSE: in PerformDAGCombine()
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| H A D | HexagonPatterns.td | 109 def HexagonPFALSE: SDNode<"HexagonISD::PFALSE", SDTVecLeaf>;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64SVEInstrInfo.td | 658 def PFALSE : sve_int_pfalse<0b000000, "pfalse">; 1172 (ZIP1_PPP_S PPR:$Ps, (PFALSE))>; 1174 (ZIP2_PPP_S PPR:$Ps, (PFALSE))>; 1176 (ZIP1_PPP_H PPR:$Ps, (PFALSE))>; 1178 (ZIP2_PPP_H PPR:$Ps, (PFALSE))>; 1180 (ZIP1_PPP_B PPR:$Ps, (PFALSE))>; 1182 (ZIP2_PPP_B PPR:$Ps, (PFALSE))>;
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| H A D | AArch64SchedA64FX.td | 3303 def : InstRW<[A64FXWrite_3Cyc_GI1], (instrs PFALSE)>;
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| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/aarch64/ |
| H A D | aarch64-sve.md | 242 ;; lanes (i.e. when the governing predicate is a PFALSE). The flags results 929 ;; - PFALSE
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| /netbsd-src/external/gpl3/gcc/dist/gcc/config/aarch64/ |
| H A D | aarch64-sve.md | 242 ;; lanes (i.e. when the governing predicate is a PFALSE). The flags results 929 ;; - PFALSE
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| /netbsd-src/external/gpl3/gcc/dist/gcc/ |
| H A D | ChangeLog-2018 | 33015 Handle PTRUE and PFALSE constants.
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| H A D | ChangeLog-2019 | 18464 with PTRUE and PFALSE.
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