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Searched refs:OutVT (Results 1 – 10 of 10) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp41 EVT OutVT = N->getValueType(0); in ExpandRes_BITCAST() local
42 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); in ExpandRes_BITCAST()
67 TLI.hasBigEndianPartOrdering(OutVT, DL)) in ExpandRes_BITCAST()
75 if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout())) in ExpandRes_BITCAST()
94 if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout())) in ExpandRes_BITCAST()
102 if (InVT.isVector() && OutVT.isInteger()) { in ExpandRes_BITCAST()
186 if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout())) in ExpandRes_BITCAST()
H A DLegalizeIntegerTypes.cpp339 EVT OutVT = N->getValueType(0); in PromoteIntRes_BITCAST() local
340 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); in PromoteIntRes_BITCAST()
418 unsigned OutSize = OutVT.getSizeInBits(); in PromoteIntRes_BITCAST()
422 OutVT.getVectorElementType(), in PromoteIntRes_BITCAST()
423 OutVT.getVectorNumElements() * Scale); in PromoteIntRes_BITCAST()
426 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, InOp, in PromoteIntRes_BITCAST()
435 CreateStackStoreLoad(InOp, OutVT)); in PromoteIntRes_BITCAST()
4636 EVT OutVT = V0.getValueType(); in PromoteIntRes_VECTOR_SPLICE() local
4638 return DAG.getNode(ISD::VECTOR_SPLICE, dl, OutVT, V0, V1, N->getOperand(2)); in PromoteIntRes_VECTOR_SPLICE()
4643 EVT OutVT = N->getValueType(0); in PromoteIntRes_EXTRACT_SUBVECTOR() local
[all …]
H A DLegalizeVectorTypes.cpp2337 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), in SplitVecOp_UnaryOp() local
2341 Lo = DAG.getNode(N->getOpcode(), dl, { OutVT, MVT::Other }, in SplitVecOp_UnaryOp()
2343 Hi = DAG.getNode(N->getOpcode(), dl, { OutVT, MVT::Other }, in SplitVecOp_UnaryOp()
2355 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo); in SplitVecOp_UnaryOp()
2356 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi); in SplitVecOp_UnaryOp()
2796 EVT OutVT = N->getValueType(0); in SplitVecOp_TruncateHelper() local
2797 ElementCount NumElements = OutVT.getVectorElementCount(); in SplitVecOp_TruncateHelper()
2798 bool IsFloat = OutVT.isFloatingPoint(); in SplitVecOp_TruncateHelper()
2801 unsigned OutElementSize = OutVT.getScalarSizeInBits(); in SplitVecOp_TruncateHelper()
2805 std::tie(LoOutVT, HiOutVT) = DAG.GetSplitDestVTs(OutVT); in SplitVecOp_TruncateHelper()
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H A DDAGCombiner.cpp20600 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), OutSVT, NumElts / Scale); in combineShuffleToVectorExtend() local
20603 if (TLI.isTypeLegal(OutVT)) in combineShuffleToVectorExtend()
20605 TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND_VECTOR_INREG, OutVT)) in combineShuffleToVectorExtend()
20608 SDLoc(SVN), OutVT, N0)); in combineShuffleToVectorExtend()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp4488 MVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(P.Operand * 8), in getPermuteNode() local
4490 Op = DAG.getNode(SystemZISD::PACK, DL, OutVT, Op0, Op1); in getPermuteNode()
4868 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(OutBits), in insertUnpackIfPrepared() local
4870 return DAG.getNode(SystemZISD::UNPACKL_HIGH, DL, OutVT, PackedOp); in insertUnpackIfPrepared()
5270 EVT OutVT = Op.getValueType(); in lowerSIGN_EXTEND_VECTOR_INREG() local
5272 unsigned ToBits = OutVT.getScalarSizeInBits(); in lowerSIGN_EXTEND_VECTOR_INREG()
5276 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(FromBits), in lowerSIGN_EXTEND_VECTOR_INREG() local
5279 DAG.getNode(SystemZISD::UNPACK_HIGH, SDLoc(PackedOp), OutVT, PackedOp); in lowerSIGN_EXTEND_VECTOR_INREG()
5289 EVT OutVT = Op.getValueType(); in lowerZERO_EXTEND_VECTOR_INREG() local
5292 unsigned OutNumElts = OutVT.getVectorNumElements(); in lowerZERO_EXTEND_VECTOR_INREG()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3751 EVT OutVT = Op.getValueType(); in lowerConvertToSVBool() local
3757 if (InVT == OutVT) in lowerConvertToSVBool()
3761 DAG.getNode(AArch64ISD::REINTERPRET_CAST, DL, OutVT, InOp); in lowerConvertToSVBool()
3776 DAG.getNode(AArch64ISD::REINTERPRET_CAST, DL, OutVT, Mask); in lowerConvertToSVBool()
3777 return DAG.getNode(ISD::AND, DL, OutVT, Reinterpret, MaskReinterpret); in lowerConvertToSVBool()
13798 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); in getPTest() local
13799 SDValue TVal = DAG.getConstant(1, DL, OutVT); in getPTest()
13800 SDValue FVal = DAG.getConstant(0, DL, OutVT); in getPTest()
13808 SDValue Res = DAG.getNode(AArch64ISD::CSEL, DL, OutVT, FVal, TVal, CC, Test); in getPTest()
15806 SDValue OutVT = DAG.getValueType(RetVT); in performGatherLoadCombine() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp20924 EVT InVT = MVT::i16, OutVT = MVT::i8; in truncateVectorWithPACK() local
20928 OutVT = MVT::i16; in truncateVectorWithPACK()
20934 OutVT = EVT::getVectorVT(Ctx, OutVT, 128 / OutVT.getSizeInBits()); in truncateVectorWithPACK()
20936 SDValue Res = DAG.getNode(Opcode, DL, OutVT, In, DAG.getUNDEF(InVT)); in truncateVectorWithPACK()
20947 OutVT = EVT::getVectorVT(Ctx, OutVT, SubSizeInBits / OutVT.getSizeInBits()); in truncateVectorWithPACK()
20953 SDValue Res = DAG.getNode(Opcode, DL, OutVT, Lo, Hi); in truncateVectorWithPACK()
20962 SDValue Res = DAG.getNode(Opcode, DL, OutVT, Lo, Hi); in truncateVectorWithPACK()
20968 int Scale = 64 / OutVT.getScalarSizeInBits(); in truncateVectorWithPACK()
20970 Res = DAG.getVectorShuffle(OutVT, DL, Res, Res, Mask); in truncateVectorWithPACK()
46466 EVT OutVT = N->getValueType(0); in combineVectorTruncationWithPACKUS() local
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H A DX86InstrSSE.td3718 multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
3729 (OutVT (OpNode (ArgVT RC:$src1), RC:$src2)))]>,
3738 (OutVT (OpNode (ArgVT RC:$src1),
3743 multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
3754 (OutVT (OpNode (ArgVT RC:$src1), RC:$src2)))]>,
3763 (OutVT (OpNode (ArgVT RC:$src1),
H A DX86InstrAVX512.td323 multiclass AVX512_maskable_3src_cast<bits<8> O, Format F, X86VectorVTInfo OutVT,
328 AVX512_maskable_common<O, F, OutVT, Outs,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp8403 EVT OutVT = Op.getValueType(); in LowerINT_TO_FP() local
8404 if (OutVT.isVector() && OutVT.isFloatingPoint() && in LowerINT_TO_FP()