| /netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | AsmWriterInst.h | 35 } OperandType; member
54 AsmWriterOperand(OpType op = isLiteralTextOperand):OperandType(op) {} in OperandType() function
58 : OperandType(op), Str(LitStr) {} in OperandType() function
63 : OperandType(op), MIOpNo(_MIOpNo), Str(Printer), MiModifier(Modifier), in OperandType() function
67 if (OperandType != Other.OperandType || Str != Other.Str) return true;
68 if (OperandType == isMachineInstrOperand)
99 Operands.back().OperandType == AsmWriterOperand::isLiteralTextOperand) in AddLiteralString()
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| H A D | AsmWriterInst.cpp | 24 if (OperandType == isLiteralTextOperand) { in getCode()
30 if (OperandType == isLiteralStatementOperand) in getCode()
181 OpInfo.OperandType == "MCOI::OPERAND_PCREL"); in AsmWriterInst()
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| H A D | WebAssemblyDisassemblerEmitter.cpp | 121 assert(Op.OperandType != "MCOI::OPERAND_UNKNOWN"); in emitWebAssemblyDisassemblerTables()
122 CurOperandList.push_back(Op.OperandType); in emitWebAssemblyDisassemblerTables()
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| H A D | CodeGenInstruction.cpp | 79 std::string OperandType = "OPERAND_UNKNOWN"; in CGIOperandList() local
85 OperandType = std::string(Rec->getValueAsString("OperandType")); in CGIOperandList()
90 OperandType = std::string(Rec->getValueAsString("OperandType")); in CGIOperandList()
118 OperandType = "OPERAND_REGISTER"; in CGIOperandList()
138 std::string(EncoderMethod), OperandNamespace + "::" + OperandType, in CGIOperandList()
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| H A D | CodeGenInstruction.h | 95 std::string OperandType; member
123 OperandType(OT), MIOperandNo(MION), MINumOperands(MINO), in OperandInfo()
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| H A D | X86DisassemblerTables.cpp | 47 static inline const char* stringForOperandType(OperandType type) { in stringForOperandType()
817 typedef SmallVector<std::pair<OperandEncoding, OperandType>, in emitInstructionInfo()
827 OperandType Type = (OperandType)Operand.type; in emitInstructionInfo()
857 OperandType Type = (OperandType)Operand.type; in emitInstructionInfo()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyInstrInfo.td | 135 let OperandType = "OPERAND_BASIC_BLOCK" in
138 let OperandType = "OPERAND_LOCAL" in
141 let OperandType = "OPERAND_GLOBAL" in {
150 let OperandType = "OPERAND_I32IMM" in
153 let OperandType = "OPERAND_I64IMM" in
156 let OperandType = "OPERAND_F32IMM" in
159 let OperandType = "OPERAND_F64IMM" in
162 let OperandType = "OPERAND_VEC_I8IMM" in
165 let OperandType = "OPERAND_VEC_I16IMM" in
168 let OperandType = "OPERAND_VEC_I32IMM" in
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| H A D | WebAssemblyMCInstLower.cpp | 265 if (Info.OperandType == WebAssembly::OPERAND_TYPEINDEX) { in lower()
289 } else if (Info.OperandType == WebAssembly::OPERAND_SIGNATURE) { in lower()
299 } else if (Info.OperandType == WebAssembly::OPERAND_HEAPTYPE) { in lower()
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| H A D | WebAssemblySetP2AlignOperands.cpp | 65 assert(MI.getDesc().OpInfo[OperandNo].OperandType == in rewriteP2Align()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/Disassembler/ |
| H A D | M68kDisassembler.cpp | 379 bool IsPCRel = Desc.OpInfo[MIOpIdx].OperandType == MCOI::OPERAND_PCREL; in getRegOperandIndex()
399 bool IsPCRel = Desc.OpInfo[MIOpIdx].OperandType == MCOI::OPERAND_PCREL; in getImmOperandIndex()
490 enum class OperandType { in getInstruction() enum
496 SmallVector<OperandType, 6> OpType(NumOperands, OperandType::Invalid); in getInstruction()
530 assert(((OpType[MIOpIdx] == OperandType::Invalid) || in getInstruction()
531 (OpType[MIOpIdx] == OperandType::Reg)) && in getInstruction()
533 OpType[MIOpIdx] = OperandType::Reg; in getInstruction()
543 assert(((OpType[MIOpIdx] == OperandType::Invalid) || in getInstruction()
544 (OpType[MIOpIdx] == OperandType::Imm)) && in getInstruction()
546 OpType[MIOpIdx] = OperandType::Imm; in getInstruction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| H A D | MCInstrDesc.h | 56 enum OperandType { enum
95 uint8_t OperandType; variable
117 return OperandType >= MCOI::OPERAND_FIRST_GENERIC && in isGenericType()
118 OperandType <= MCOI::OPERAND_LAST_GENERIC; in isGenericType()
123 return OperandType - MCOI::OPERAND_FIRST_GENERIC; in getGenericTypeIndex()
127 return OperandType >= MCOI::OPERAND_FIRST_GENERIC_IMM && in isGenericImm()
128 OperandType <= MCOI::OPERAND_LAST_GENERIC_IMM; in isGenericImm()
133 return OperandType - MCOI::OPERAND_FIRST_GENERIC_IMM; in getGenericImmIndex()
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| /netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/ |
| H A D | SnippetGenerator.cpp | 230 if (Op.getExplicitOperandInfo().OperandType >= in randomizeMCOperand()
231 MCOI::OperandType::OPERAND_FIRST_TARGET) in randomizeMCOperand()
234 switch (Op.getExplicitOperandInfo().OperandType) { in randomizeMCOperand()
235 case MCOI::OperandType::OPERAND_IMMEDIATE: in randomizeMCOperand()
239 case MCOI::OperandType::OPERAND_REGISTER: { in randomizeMCOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.h | 115 enum OperandType { enum
119 inline bool isVpred(OperandType op) { in isVpred()
123 return isVpred(static_cast<OperandType>(op)); in isVpred()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
| H A D | WebAssemblyMCCodeEmitter.cpp | 97 << int(Info.OperandType) << "\n"); in encodeInstruction()
98 switch (Info.OperandType) { in encodeInstruction()
143 switch (Info.OperandType) { in encodeInstruction()
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| /netbsd-src/external/apache2/llvm/dist/clang/include/clang/Sema/ |
| H A D | DelayedDiagnostic.h | 163 DD.ForbiddenTypeData.OperandType = type.getAsOpaquePtr(); in makeForbiddenType()
218 return QualType::getFromOpaquePtr(ForbiddenTypeData.OperandType); in getForbiddenTypeOperand()
250 void *OperandType; member
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/DebugInfo/DWARF/ |
| H A D | DWARFDebugFrame.cpp | 381 const char *CFIProgram::operandTypeString(CFIProgram::OperandType OT) { in operandTypeString()
406 OperandType Type = CFIP.getOperandTypes()[Opcode][OperandIdx]; in getOperandAsUnsigned()
450 OperandType Type = CFIP.getOperandTypes()[Opcode][OperandIdx]; in getOperandAsSigned()
758 ArrayRef<CFIProgram::OperandType[2]> CFIProgram::getOperandTypes() { in getOperandTypes()
759 static OperandType OpTypes[DW_CFA_restore+1][2]; in getOperandTypes()
762 return ArrayRef<OperandType[2]>(&OpTypes[0], DW_CFA_restore+1); in getOperandTypes()
808 return ArrayRef<OperandType[2]>(&OpTypes[0], DW_CFA_restore+1); in getOperandTypes()
818 OperandType Type = getOperandTypes()[Opcode][OperandIdx]; in printOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/X86/ |
| H A D | Target.cpp | 221 Op.getExplicitOperandInfo().OperandType == MCOI::OPERAND_PCREL) in isInvalidOpcode()
812 switch (Op.getExplicitOperandInfo().OperandType) { in randomizeTargetMCOperand()
813 case X86::OperandType::OPERAND_ROUNDING_CONTROL: in randomizeTargetMCOperand()
822 .concat(Twine(Op.getExplicitOperandInfo().OperandType))); in randomizeTargetMCOperand()
914 switch (Instr.getPrimaryOperand(Var).getExplicitOperandInfo().OperandType) { in generateInstructionVariants()
919 case X86::OperandType::OPERAND_COND_CODE: { in generateInstructionVariants()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.td | 908 let OperandType = opType#"_INT16";
914 let OperandType = opType#"_FP16";
920 let OperandType = opType#"_INT32";
926 let OperandType = opType#"_FP32";
932 let OperandType = opType#"_V2INT16";
938 let OperandType = opType#"_V2FP16";
949 let OperandType = opType#"_INT64";
954 let OperandType = opType#"_FP64";
960 let OperandType = opType#"_V2FP32";
966 let OperandType = opType#"_V2INT32";
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| H A D | SIInstrInfo.h | 760 bool isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const;
764 return isInlineConstant(MO, OpInfo.OperandType); in isInlineConstant()
785 return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType); in isInlineConstant()
802 return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType); in isInlineConstant()
812 return MO.isImm() && !isInlineConstant(MO, OpInfo.OperandType); in isLiteralConstant()
873 assert(OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE); in getOpSize()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsBaseInfo.h | 132 enum OperandType : unsigned { enum
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/DebugInfo/DWARF/ |
| H A D | DWARFDebugFrame.h | 476 enum OperandType { enum
489 static const char *operandTypeString(OperandType OT);
493 static ArrayRef<OperandType[2]> getOperandTypes();
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/MCTargetDesc/ |
| H A D | M68kMCCodeEmitter.cpp | 138 bool IsPCRel = Desc.OpInfo[MIOpIdx].OperandType == MCOI::OPERAND_PCREL; in encodeReg()
199 bool IsPCRel = Desc.OpInfo[MIOpIdx].OperandType == MCOI::OPERAND_PCREL; in encodeImm()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/Disassembler/ |
| H A D | X86Disassembler.cpp | 740 static uint16_t name(struct InternalInstruction *insn, OperandType type, \
847 (Reg)fixupRegValue(insn, (OperandType)op->type, insn->vvvv, &valid); in fixupReg()
852 insn->reg = (Reg)fixupRegValue(insn, (OperandType)op->type, in fixupReg()
861 insn, (OperandType)op->type, insn->eaBase - insn->eaRegBase, &valid); in fixupReg()
1520 switch ((OperandType)Op.type) { in readOperands()
1887 OperandType type = (OperandType)operand.type; in translateImmediate()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MicroMipsInstrInfo.td | 69 let OperandType = "OPERAND_MEMORY";
102 let OperandType = "OPERAND_MEMORY";
110 let OperandType = "OPERAND_MEMORY";
120 let OperandType = "OPERAND_MEMORY";
128 let OperandType = "OPERAND_MEMORY";
136 let OperandType = "OPERAND_MEMORY";
145 let OperandType = "OPERAND_MEMORY";
161 let OperandType = "OPERAND_MEMORY";
174 let OperandType = "OPERAND_PCREL";
181 let OperandType = "OPERAND_PCREL";
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/MCTargetDesc/ |
| H A D | LanaiMCTargetDesc.cpp | 101 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType == in evaluateBranch()
|