| /netbsd-src/external/apache2/llvm/dist/llvm/lib/DebugInfo/DWARF/ |
| H A D | DWARFDebugFrame.cpp | 401 uint32_t OperandIdx) const { in getOperandAsUnsigned()
402 if (OperandIdx >= 2) in getOperandAsUnsigned()
405 OperandIdx); in getOperandAsUnsigned()
406 OperandType Type = CFIP.getOperandTypes()[Opcode][OperandIdx]; in getOperandAsUnsigned()
407 uint64_t Operand = Ops[OperandIdx]; in getOperandAsUnsigned()
414 OperandIdx, CFIProgram::operandTypeString(Type)); in getOperandAsUnsigned()
423 OperandIdx); in getOperandAsUnsigned()
436 OperandIdx); in getOperandAsUnsigned()
445 uint32_t OperandIdx) const { in getOperandAsSigned()
446 if (OperandIdx >= 2) in getOperandAsSigned()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | R600Packetizer.cpp | 81 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write); in getPreviousVector() local
82 if (OperandIdx > -1 && BI->getOperand(OperandIdx).getImm() == 0) in getPreviousVector()
131 int OperandIdx = TII->getOperandIdx(MI.getOpcode(), Ops[i]); in substitutePV() local
132 if (OperandIdx < 0) in substitutePV()
134 Register Src = MI.getOperand(OperandIdx).getReg(); in substitutePV()
137 MI.getOperand(OperandIdx).setReg(It->second); in substitutePV()
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| H A D | R600ISelLowering.cpp | 2123 int OperandIdx[] = { in PostISelFolding() local
2154 if (OperandIdx[i] < 0) in PostISelFolding()
2156 SDValue &Src = Ops[OperandIdx[i] - 1]; in PostISelFolding()
2160 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]); in PostISelFolding()
2176 int OperandIdx[] = { in PostISelFolding() local
2192 if (OperandIdx[i] < 0) in PostISelFolding()
2194 SDValue &Src = Ops[OperandIdx[i] - 1]; in PostISelFolding()
2199 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]); in PostISelFolding()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| H A D | MCInstrItineraries.h | 167 int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const { in getOperandCycle() argument
173 if ((FirstIdx + OperandIdx) >= LastIdx) in getOperandCycle()
176 return (int)OperandCycles[FirstIdx + OperandIdx]; in getOperandCycle()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/ |
| H A D | CanonicalizeFreezeInLoops.cpp | 187 unsigned OperandIdx = in run() local
189 InsertFreezeAndForgetFromSCEV(PHI->getOperandUse(OperandIdx)); in run()
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| H A D | ScalarEvolutionExpander.cpp | 2401 WorkItem.ParentOpcode, WorkItem.OperandIdx, Imm, Ty, CostKind); in isHighCostExpansionHelper()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/DebugInfo/DWARF/ |
| H A D | DWARFDebugFrame.h | 405 uint32_t OperandIdx) const;
408 uint32_t OperandIdx) const;
498 const Instruction &Instr, unsigned OperandIdx,
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Transforms/Utils/ |
| H A D | ScalarEvolutionExpander.h | 48 ParentOpcode(Opc), OperandIdx(Idx), S(S) { } in SCEVOperand()
52 int OperandIdx; member
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 838 unsigned OperandIdx = 0; in EmitDbgInstrRef() local
842 ++OperandIdx; in EmitDbgInstrRef()
844 assert(OperandIdx < DefMI.getNumOperands()); in EmitDbgInstrRef()
849 MIB.addImm(OperandIdx); in EmitDbgInstrRef()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
| H A D | RewriteStatepointsForGC.cpp | 1173 auto UpdateOperand = [&](int OperandIdx) { in findBasePointer() argument
1174 Value *InVal = BdvIE->getOperand(OperandIdx); in findBasePointer()
1176 BaseIE->setOperand(OperandIdx, Base); in findBasePointer()
1183 auto UpdateOperand = [&](int OperandIdx) { in findBasePointer() argument
1184 Value *InVal = BdvSV->getOperand(OperandIdx); in findBasePointer()
1186 BaseSV->setOperand(OperandIdx, Base); in findBasePointer()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 5888 unsigned OperandIdx[4]; in cvtExp() local
5898 OperandIdx[SrcIdx] = Inst.size(); in cvtExp()
5906 OperandIdx[SrcIdx] = Inst.size(); in cvtExp()
5929 Inst.getOperand(OperandIdx[1]) = Inst.getOperand(OperandIdx[2]); in cvtExp()
5930 Inst.getOperand(OperandIdx[2]).setReg(AMDGPU::NoRegister); in cvtExp()
5931 Inst.getOperand(OperandIdx[3]).setReg(AMDGPU::NoRegister); in cvtExp()
5935 if (Inst.getOperand(OperandIdx[i]).getReg() != AMDGPU::NoRegister) { in cvtExp()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 1791 unsigned OperandIdx = 1; in ParseInstruction() local
1800 ++OperandIdx; in ParseInstruction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | CodeGenPrepare.cpp | 7194 unsigned OperandIdx) { in canCauseUndefinedBehavior() argument
7197 if (OperandIdx != 1) in canCauseUndefinedBehavior()
|