| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsRegisterBankInfo.h | 75 bool isAmbiguous_64(InstType InstTy, unsigned OpSize) const { in isAmbiguous_64() argument
76 if (InstTy == InstType::Ambiguous && OpSize == 64) in isAmbiguous_64()
81 bool isAmbiguous_32(InstType InstTy, unsigned OpSize) const { in isAmbiguous_32() argument
82 if (InstTy == InstType::Ambiguous && OpSize == 32) in isAmbiguous_32()
87 bool isAmbiguous_32or64(InstType InstTy, unsigned OpSize) const { in isAmbiguous_32or64() argument
88 if (InstTy == InstType::Ambiguous && (OpSize == 32 || OpSize == 64)) in isAmbiguous_32or64()
94 unsigned OpSize) const { in isAmbiguousWithMergeOrUnmerge_64() argument
95 if (InstTy == InstType::AmbiguousWithMergeOrUnmerge && OpSize == 64) in isAmbiguousWithMergeOrUnmerge_64()
100 bool isFloatingPoint_32or64(InstType InstTy, unsigned OpSize) const { in isFloatingPoint_32or64() argument
101 if (InstTy == InstType::FloatingPoint && (OpSize == 32 || OpSize == 64)) in isFloatingPoint_32or64()
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| /netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | X86RecognizableInstr.h | 177 uint8_t OpSize; variable
248 bool hasREX_WPrefix, uint8_t OpSize);
259 uint8_t OpSize);
264 uint8_t OpSize);
269 uint8_t OpSize);
271 uint8_t OpSize);
273 uint8_t OpSize);
275 uint8_t OpSize);
277 uint8_t OpSize);
279 uint8_t OpSize);
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| H A D | X86RecognizableInstr.cpp | 82 OpSize = byteFromRec(Rec, "OpSizeBits"); in RecognizableInstr()
295 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) in insnContext()
299 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) in insnContext()
301 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) in insnContext()
305 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32) in insnContext()
307 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) in insnContext()
324 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) in insnContext()
326 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) in insnContext()
334 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16) in insnContext()
336 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) in insnContext()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMLegalizerInfo.cpp | 399 auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); in legalizeCustom() local
404 auto Libcalls = getFCmpLibcalls(Predicate, OpSize); in legalizeCustom()
416 assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size"); in legalizeCustom()
417 auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx); in legalizeCustom()
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| H A D | ARMInstructionSelector.cpp | 460 unsigned OpRegBank, unsigned OpSize) in CmpConstants()
463 OperandSize(OpSize) {} in CmpConstants()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/IR/ |
| H A D | Metadata.cpp | 495 size_t OpSize = NumOps * sizeof(MDOperand); in operator new() local
498 OpSize = alignTo(OpSize, alignof(uint64_t)); in operator new()
499 void *Ptr = reinterpret_cast<char *>(::operator new(OpSize + Size)) + OpSize; in operator new()
510 size_t OpSize = N->NumOperands * sizeof(MDOperand); in operator delete() local
511 OpSize = alignTo(OpSize, alignof(uint64_t)); in operator delete()
516 ::operator delete(reinterpret_cast<char *>(Mem) - OpSize); in operator delete()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 664 SmallVector<unsigned, 4> OpSize(NumOperands); in getInstrMapping() local
672 OpSize[Idx] = Ty.getSizeInBits(); in getInstrMapping()
740 OpSize[0]); in getInstrMapping()
965 auto Mapping = getValueMapping(OpRegBankIdx[Idx], OpSize[Idx]); in getInstrMapping()
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| H A D | AArch64InstructionSelector.cpp | 665 unsigned OpSize) { in selectBinaryOp() argument
668 if (OpSize == 32) { in selectBinaryOp()
679 } else if (OpSize == 64) { in selectBinaryOp()
695 switch (OpSize) { in selectBinaryOp()
736 unsigned OpSize) { in selectLoadStoreUIOp() argument
740 switch (OpSize) { in selectLoadStoreUIOp()
752 switch (OpSize) { in selectLoadStoreUIOp()
2754 const unsigned OpSize = Ty.getSizeInBits(); in select() local
2759 const unsigned NewOpc = selectBinaryOp(I.getOpcode(), RB.getID(), OpSize); in select()
4284 unsigned OpSize = Ty.getSizeInBits(); in emitFPCompare() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | GISelKnownBits.cpp | 456 unsigned OpSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); in computeKnownBitsImpl() local
462 Known.insertBits(SrcOpKnown, I * OpSize); in computeKnownBitsImpl()
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| H A D | MachineIRBuilder.cpp | 558 unsigned OpSize = OpTy.getSizeInBits(); in buildSequence() local
561 if (getMRI()->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) { in buildSequence()
567 if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) { in buildSequence()
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| H A D | LegalizerHelper.cpp | 4899 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); in narrowScalarExtract() local
4903 if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) { in narrowScalarExtract()
4918 SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart); in narrowScalarExtract()
4921 SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize); in narrowScalarExtract()
4968 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); in narrowScalarInsert() local
4972 if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) { in narrowScalarInsert()
4990 SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart); in narrowScalarInsert()
4995 std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart); in narrowScalarInsert()
4999 if (ExtractOffset != 0 || SegSize != OpSize) { in narrowScalarInsert()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 584 int64_t OpSize = MFI.getObjectSize(FI); in foldMemoryOperand() local
589 OpSize = SubRegSize / 8; in foldMemoryOperand()
592 MemSize = std::max(MemSize, OpSize); in foldMemoryOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/ObjectYAML/ |
| H A D | DWARFEmitter.cpp | 836 if (Expected<uint64_t> OpSize = in writeListEntry() local
838 DescriptionsLength += *OpSize; in writeListEntry()
840 return OpSize.takeError(); in writeListEntry()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 850 unsigned OpSize = OpTy.getSizeInBits(); in executeInWaterfallLoop() local
853 if (OpSize == 32) { in executeInWaterfallLoop()
894 bool Is64 = OpSize % 64 == 0; in executeInWaterfallLoop()
896 LLT UnmergeTy = OpSize % 64 == 0 ? LLT::scalar(64) : LLT::scalar(32); in executeInWaterfallLoop()
897 unsigned CmpOp = OpSize % 64 == 0 ? AMDGPU::V_CMP_EQ_U64_e64 in executeInWaterfallLoop()
4025 unsigned OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); in getInstrMapping() local
4026 OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, OpSize); in getInstrMapping()
4027 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, OpSize); in getInstrMapping()
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| H A D | SIISelLowering.cpp | 3102 unsigned OpSize = Flags.isByVal() ? in LowerCall() local
3112 int FI = MFI.CreateFixedObject(OpSize, Offset, true); in LowerCall()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrFormats.td | 192 class OpSize16 { OperandSize OpSize = OpSize16; }
193 class OpSize32 { OperandSize OpSize = OpSize32; }
294 OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change
296 bits<2> OpSizeBits = OpSize.Value;
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| H A D | X86InstrArithmetic.td | 594 /// OpSize - Selects whether the instruction needs a 0x66 prefix based on
597 OperandSize OpSize = opSize;
636 let OpSize = typeinfo.OpSize;
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| H A D | X86ISelLowering.cpp | 4274 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; in LowerCall() local
4275 FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true); in LowerCall()
48240 unsigned OpSize = OpVT.getSizeInBits(); in combineVectorSizedSetCCEquality() local
48241 if (!OpVT.isScalarInteger() || OpSize < 128) in combineVectorSizedSetCCEquality()
48269 if ((OpSize == 128 && Subtarget.hasSSE2()) || in combineVectorSizedSetCCEquality()
48270 (OpSize == 256 && Subtarget.hasAVX()) || in combineVectorSizedSetCCEquality()
48271 (OpSize == 512 && Subtarget.useAVX512Regs())) { in combineVectorSizedSetCCEquality()
48278 bool NeedZExt = PreferKOT && !Subtarget.hasVLX() && OpSize != 512; in combineVectorSizedSetCCEquality()
48282 if (OpSize == 256) { in combineVectorSizedSetCCEquality()
48288 if (OpSize == 512 || NeedZExt) { in combineVectorSizedSetCCEquality()
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| H A D | X86InstrSSE.td | 1656 // SSE2 instructions without OpSize prefix
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| H A D | ConstantFolding.cpp | 788 unsigned OpSize = DL.getTypeSizeInBits(Op0->getType()); in SymbolicallyEvaluateBinop() local
793 return ConstantInt::get(Op0->getType(), Offs1.zextOrTrunc(OpSize) - in SymbolicallyEvaluateBinop()
794 Offs2.zextOrTrunc(OpSize)); in SymbolicallyEvaluateBinop()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 681 uint32_t OpSize = (VA.getLocVT().getSizeInBits() + 7) / 8; in LowerCall() local
682 FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true); in LowerCall()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 5775 unsigned OpSize; in LowerCall() local
5777 OpSize = VA.getLocVT().getFixedSizeInBits(); in LowerCall()
5779 OpSize = Flags.isByVal() ? Flags.getByValSize() * 8 in LowerCall()
5781 OpSize = (OpSize + 7) / 8; in LowerCall()
5784 if (OpSize < 8) in LowerCall()
5785 BEAlign = 8 - OpSize; in LowerCall()
5794 int FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true); in LowerCall()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 3166 auto OpSize = AMDGPU::getOperandSize(Desc, OpIdx); in isInlineConstant() local
3168 switch (OpSize) { // expected operand size in isInlineConstant()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 4971 uint32_t OpSize = (Arg.getValueSizeInBits() + 7) / 8; in CalculateTailCallArgDest() local
4972 int FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true); in CalculateTailCallArgDest()
12968 auto OpSize = N->getOperand(0).getValueSizeInBits(); in ConvertSETCCToSubtract() local
12972 if (OpSize < Size) { in ConvertSETCCToSubtract()
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| /netbsd-src/external/apache2/llvm/dist/llvm/docs/TableGen/ |
| H A D | ProgRef.rst | 1954 OperandSize OpSize = OpSize32;
|