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Searched refs:OpName (Results 1 – 25 of 67) sorted by relevance

123

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.cpp67 NewMI->getOperand(getOperandIdx(*NewMI, R600::OpName::src0)) in copyPhysReg()
133 return isLDSInstr(Opcode) && getOperandIdx(Opcode, R600::OpName::dst) != -1; in isLDSRetInstr()
233 {R600::OpName::src0, R600::OpName::src0_sel}, in getSelIdx()
234 {R600::OpName::src1, R600::OpName::src1_sel}, in getSelIdx()
235 {R600::OpName::src2, R600::OpName::src2_sel}, in getSelIdx()
236 {R600::OpName::src0_X, R600::OpName::src0_sel_X}, in getSelIdx()
237 {R600::OpName::src0_Y, R600::OpName::src0_sel_Y}, in getSelIdx()
238 {R600::OpName::src0_Z, R600::OpName::src0_sel_Z}, in getSelIdx()
239 {R600::OpName::src0_W, R600::OpName::src0_sel_W}, in getSelIdx()
240 {R600::OpName::src1_X, R600::OpName::src1_sel_X}, in getSelIdx()
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H A DSIPeepholeSDWA.cpp308 if (TII->getNamedOperand(*MI, AMDGPU::OpName::src0) == SrcOp) { in getSrcMods()
309 if (auto *Mod = TII->getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) { in getSrcMods()
312 } else if (TII->getNamedOperand(*MI, AMDGPU::OpName::src1) == SrcOp) { in getSrcMods()
313 if (auto *Mod = TII->getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers)) { in getSrcMods()
343 MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in convertToSDWA()
344 MachineOperand *SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src0_sel); in convertToSDWA()
346 TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers); in convertToSDWA()
350 Src = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in convertToSDWA()
351 SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src1_sel); in convertToSDWA()
352 SrcMods = TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers); in convertToSDWA()
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H A DGCNDPPCombine.cpp126 if (const auto *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) { in isShrinkable()
135 if (!hasNoImmOrEqual(MI, AMDGPU::OpName::src0_modifiers, 0, Mask) || in isShrinkable()
136 !hasNoImmOrEqual(MI, AMDGPU::OpName::src1_modifiers, 0, Mask) || in isShrinkable()
137 !hasNoImmOrEqual(MI, AMDGPU::OpName::clamp, 0) || in isShrinkable()
138 !hasNoImmOrEqual(MI, AMDGPU::OpName::omod, 0)) { in isShrinkable()
201 auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst); in createDPPInst()
206 const int OldIdx = AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::old); in createDPPInst()
212 TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst)->getReg()), in createDPPInst()
227 AMDGPU::OpName::src0_modifiers)) { in createDPPInst()
229 AMDGPU::OpName::src0_modifiers)); in createDPPInst()
[all …]
H A DR600ExpandSpecialInstrs.cpp86 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in runOnMachineFunction()
93 R600::OpName::pred_sel); in runOnMachineFunction()
95 R600::OpName::pred_sel); in runOnMachineFunction()
115 TII->setImmOperand(*PredSet, R600::OpName::update_exec_mask, 1); in runOnMachineFunction()
117 TII->setImmOperand(*PredSet, R600::OpName::update_pred, 1); in runOnMachineFunction()
147 BMI->getOperand(TII->getOperandIdx(Opcode, R600::OpName::src0)) in runOnMachineFunction()
150 BMI->getOperand(TII->getOperandIdx(Opcode, R600::OpName::src1)) in runOnMachineFunction()
197 MI.getOperand(TII->getOperandIdx(MI, R600::OpName::dst)).getReg(); in runOnMachineFunction()
199 MI.getOperand(TII->getOperandIdx(MI, R600::OpName::src0)).getReg(); in runOnMachineFunction()
204 int Src1Idx = TII->getOperandIdx(MI, R600::OpName::src1); in runOnMachineFunction()
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H A DSILoadStoreOptimizer.cpp292 TII.getNamedOperand(MI, AMDGPU::OpName::dmask)->getImm(); in getOpcodeWidth()
343 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr) == -1 && in getInstClass()
344 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0) == -1) in getInstClass()
441 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0); in getRegs()
443 int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::srsrc); in getRegs()
517 DMask = TII.getNamedOperand(*I, AMDGPU::OpName::dmask)->getImm(); in setMI()
521 int OffsetIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::offset); in setMI()
526 Format = TII.getNamedOperand(*I, AMDGPU::OpName::format)->getImm(); in setMI()
533 CPol = TII.getNamedOperand(*I, AMDGPU::OpName::cpol)->getImm(); in setMI()
541 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0) + J; in setMI()
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H A DR600ClauseMergePass.cpp78 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT)) in getCFAluSize()
85 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled)) in isCFAluEnabled()
91 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); in cleanPotentialDisabledCFAlu()
110 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); in mergeIfPossible()
122 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE0); in mergeIfPossible()
124 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK0); in mergeIfPossible()
126 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR0); in mergeIfPossible()
138 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE1); in mergeIfPossible()
140 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK1); in mergeIfPossible()
142 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR1); in mergeIfPossible()
H A DSIFoldOperands.cpp162 int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2); in isInlineConstantIfFolded()
183 AMDGPU::OpName::vaddr); in frameIndexMayFold()
188 AMDGPU::OpName::saddr); in frameIndexMayFold()
193 AMDGPU::OpName::vaddr); in frameIndexMayFold()
219 if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0)) in updateOperand()
220 ModIdx = AMDGPU::OpName::src0_modifiers; in updateOperand()
221 else if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1)) in updateOperand()
222 ModIdx = AMDGPU::OpName::src1_modifiers; in updateOperand()
223 else if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2)) in updateOperand()
224 ModIdx = AMDGPU::OpName::src2_modifiers; in updateOperand()
[all …]
H A DSIInstrInfo.cpp83 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) { in nodesHaveSameOperandValue() argument
87 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName); in nodesHaveSameOperandValue()
88 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName); in nodesHaveSameOperandValue()
155 int Offset0Idx = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset); in areLoadsFromSameBasePtr()
156 int Offset1Idx = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset); in areLoadsFromSameBasePtr()
173 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::sbase) == -1 || in areLoadsFromSameBasePtr()
174 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::sbase) == -1) in areLoadsFromSameBasePtr()
200 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) || in areLoadsFromSameBasePtr()
201 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) || in areLoadsFromSameBasePtr()
202 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc)) in areLoadsFromSameBasePtr()
[all …]
H A DR600Packetizer.cpp81 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write); in getPreviousVector()
84 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst); in getPreviousVector()
126 R600::OpName::src0, in substitutePV()
127 R600::OpName::src1, in substitutePV()
128 R600::OpName::src2 in substitutePV()
182 int OpI = TII->getOperandIdx(MII->getOpcode(), R600::OpName::pred_sel), in isLegalToPacketizeTogether()
183 OpJ = TII->getOperandIdx(MIJ->getOpcode(), R600::OpName::pred_sel); in isLegalToPacketizeTogether()
217 unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), R600::OpName::last); in setIsLastBit()
298 R600::OpName::bank_swizzle); in addToPacket()
302 TII->getOperandIdx(MI.getOpcode(), R600::OpName::bank_swizzle); in addToPacket()
H A DR600ISelLowering.cpp276 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in EmitInstrWithCustomInserter()
336 int Idx = TII->getOperandIdx(*MIB, R600::OpName::literal); in EmitInstrWithCustomInserter()
345 TII->setImmOperand(*NewMI, R600::OpName::src0_sel, in EmitInstrWithCustomInserter()
2003 bool HasDst = TII->getOperandIdx(Opcode, R600::OpName::dst) > -1; in FoldOperand()
2014 TII->getOperandIdx(Opcode, R600::OpName::src0), in FoldOperand()
2015 TII->getOperandIdx(Opcode, R600::OpName::src1), in FoldOperand()
2016 TII->getOperandIdx(Opcode, R600::OpName::src2), in FoldOperand()
2017 TII->getOperandIdx(Opcode, R600::OpName::src0_X), in FoldOperand()
2018 TII->getOperandIdx(Opcode, R600::OpName::src0_Y), in FoldOperand()
2019 TII->getOperandIdx(Opcode, R600::OpName::src0_Z), in FoldOperand()
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H A DVOP2Instructions.td108 class VOP2_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
109 VOP_SDWA_Pseudo <OpName, P, pattern> {
113 class VOP2_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
114 VOP_DPP_Pseudo <OpName, P, pattern> {
205 string OpName, string opnd> :
206 InstAlias <OpName#" "#!subst("vcc", opnd, ps.Pfl.Asm32),
212 multiclass VOP2bInstAliases<VOP2_Pseudo ps, VOP2_Real inst, string OpName> {
214 def : VOP2bInstAlias<ps, inst, OpName, "vcc_lo">;
217 def : VOP2bInstAlias<ps, inst, OpName, "vcc">;
247 InstAlias <ps.OpName#" "#ps.Pfl.Asm32#", "#opnd,
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H A DSIOptimizeExecMaskingPreRA.cpp155 MachineOperand *Op1 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src0); in optimizeVcndVcmpPair()
156 MachineOperand *Op2 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src1); in optimizeVcndVcmpPair()
167 if (TII->hasModifiersSet(*Sel, AMDGPU::OpName::src0_modifiers) || in optimizeVcndVcmpPair()
168 TII->hasModifiersSet(*Sel, AMDGPU::OpName::src1_modifiers)) in optimizeVcndVcmpPair()
171 Op1 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src0); in optimizeVcndVcmpPair()
172 Op2 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src1); in optimizeVcndVcmpPair()
173 MachineOperand *CC = TII->getNamedOperand(*Sel, AMDGPU::OpName::src2); in optimizeVcndVcmpPair()
H A DSIRegisterInfo.cpp637 AMDGPU::OpName::offset); in getScratchInstrOffset()
647 AMDGPU::OpName::vaddr) || in getFrameIndexInstrOffset()
649 AMDGPU::OpName::saddr))) && in getFrameIndexInstrOffset()
739 TII->getNamedOperand(MI, IsFlat ? AMDGPU::OpName::saddr in resolveFrameIndex()
740 : AMDGPU::OpName::vaddr); in resolveFrameIndex()
742 MachineOperand *OffsetOp = TII->getNamedOperand(MI, AMDGPU::OpName::offset); in resolveFrameIndex()
758 MachineOperand *SOffset = TII->getNamedOperand(MI, AMDGPU::OpName::soffset); in resolveFrameIndex()
964 const MachineOperand *Reg = TII->getNamedOperand(*MI, AMDGPU::OpName::vdata); in buildMUBUFOffsetLoadStore()
971 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc)) in buildMUBUFOffsetLoadStore()
972 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)) in buildMUBUFOffsetLoadStore()
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H A DGCNHazardRecognizer.cpp127 AMDGPU::OpName::gds); in isSendMsgTraceDataOrGDS()
143 AMDGPU::OpName::simm16); in getHWReg()
717 int VDataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata); in createsVALUHazard()
730 TII->getNamedOperand(MI, AMDGPU::OpName::soffset); in createsVALUHazard()
743 int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::srsrc); in createsVALUHazard()
750 int DataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata); in createsVALUHazard()
831 TII->getNamedOperand(*RWLane, AMDGPU::OpName::src1); in checkRWLaneHazards()
896 auto *Src0 = TII->getNamedOperand(*MI, AMDGPU::OpName::src0); in fixVcmpxPermlaneHazards()
964 SDSTName = AMDGPU::OpName::vdst; in fixSMEMtoVectorWriteHazards()
967 SDSTName = AMDGPU::OpName::sdst; in fixSMEMtoVectorWriteHazards()
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H A DSIInsertWaitcnts.cpp525 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::addr); in updateByEvent()
534 AMDGPU::OpName::data0) != -1) { in updateByEvent()
537 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data0), in updateByEvent()
541 AMDGPU::OpName::data1) != -1) { in updateByEvent()
544 AMDGPU::OpName::data1), in updateByEvent()
568 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data), in updateByEvent()
573 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data), in updateByEvent()
582 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data), in updateByEvent()
595 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data), in updateByEvent()
626 MachineOperand *MO = TII->getNamedOperand(Inst, AMDGPU::OpName::data); in updateByEvent()
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H A DSIShrinkInstructions.cpp66 int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0); in foldImmediates()
225 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); in shrinkMIMG()
266 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); in shrinkMIMG()
267 int LWEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::lwe); in shrinkMIMG()
299 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdata), in shrinkMIMG()
758 TII->getNamedOperand(MI, AMDGPU::OpName::src2); in runOnMachineFunction()
772 AMDGPU::OpName::sdst); in runOnMachineFunction()
776 AMDGPU::OpName::src2); in runOnMachineFunction()
H A DVOPInstructions.td30 string OpName = opName;
611 class VOP_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
612 InstSI <P.OutsDPP, P.InsDPP, OpName#P.AsmDPP, pattern>,
613 VOP <OpName>,
614 SIMCInstr <OpName#"_dpp", SIEncodingFamily.NONE> {
634 string Mnemonic = OpName;
678 class VOP_DPP <string OpName, VOPProfile P, bit IsDPP16,
681 InstSI <P.OutsDPP, InsDPP, OpName#AsmDPP, []>,
712 class VOP_DPP8<string OpName, VOPProfile P> :
713 InstSI<P.OutsDPP8, P.InsDPP8, OpName#P.AsmDPP8, []>,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp296 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 in decodeOperand_AVLdSt_Any()
297 : AMDGPU::OpName::vdata; in decodeOperand_AVLdSt_Any()
301 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); in decodeOperand_AVLdSt_Any()
307 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); in decodeOperand_AVLdSt_Any()
406 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); in isValidDPP8()
437 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) in getInstruction()
543 AMDGPU::OpName::src2_modifiers); in getInstruction()
549 AMDGPU::OpName::cpol); in getInstruction()
556 AMDGPU::OpName::cpol); in getInstruction()
568 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); in getInstruction()
[all …]
/netbsd-src/external/apache2/llvm/dist/clang/lib/Tooling/Transformer/
H A DParsing.cpp252 std::string OpName = std::move(Id->Value); in parseRangeSelectorImpl() local
253 if (auto Op = findOptional(getUnaryStringSelectors(), OpName)) in parseRangeSelectorImpl()
256 if (auto Op = findOptional(getUnaryRangeSelectors(), OpName)) in parseRangeSelectorImpl()
259 if (auto Op = findOptional(getBinaryStringSelectors(), OpName)) in parseRangeSelectorImpl()
262 if (auto Op = findOptional(getBinaryRangeSelectors(), OpName)) in parseRangeSelectorImpl()
265 return makeParseError(State, "unknown selector name: " + OpName); in parseRangeSelectorImpl()
H A DStencil.cpp120 StringRef OpName; in toStringData() local
123 OpName = "expression"; in toStringData()
126 OpName = "deref"; in toStringData()
129 OpName = "maybeDeref"; in toStringData()
132 OpName = "addressOf"; in toStringData()
135 OpName = "maybeAddressOf"; in toStringData()
138 OpName = "describe"; in toStringData()
141 return (OpName + "(\"" + Data.Id + "\")").str(); in toStringData()
/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DCodeGenInstruction.cpp185 StringRef OpName = Op.substr(1); in ParseOperandName() local
189 StringRef::size_type DotIdx = OpName.find_first_of('.'); in ParseOperandName()
191 SubOpName = OpName.substr(DotIdx+1); in ParseOperandName()
196 OpName = OpName.substr(0, DotIdx); in ParseOperandName()
199 unsigned OpIdx = getOperandNamed(OpName); in ParseOperandName()
346 StringRef OpName; in ProcessDisableEncoding() local
347 std::tie(OpName, DisableEncoding) = getToken(DisableEncoding, " ,\t"); in ProcessDisableEncoding()
348 if (OpName.empty()) break; in ProcessDisableEncoding()
351 std::pair<unsigned,unsigned> Op = ParseOperandName(OpName, false); in ProcessDisableEncoding()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp3071 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::dst_sel); in checkTargetMatchPredicate()
3248 if (AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::imm) != -1) { in validateConstantBusLimitations()
3259 const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0); in validateConstantBusLimitations()
3260 const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); in validateConstantBusLimitations()
3261 const int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2); in validateConstantBusLimitations()
3327 const int DstIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdst); in validateEarlyClobberLimitations()
3335 const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0); in validateEarlyClobberLimitations()
3336 const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); in validateEarlyClobberLimitations()
3337 const int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2); in validateEarlyClobberLimitations()
3368 int ClampIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp); in validateIntClampSupported()
[all …]
/netbsd-src/external/apache2/llvm/dist/clang/lib/AST/
H A DDeclarationName.cpp177 const char *OpName = getOperatorSpelling(getCXXOverloadedOperator()); in print() local
178 assert(OpName && "not an overloaded operator"); in print()
181 if (OpName[0] >= 'a' && OpName[0] <= 'z') in print()
183 OS << OpName; in print()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp305 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format); in printSymbolicFormat()
715 AMDGPU::OpName::src1)) in printOperand()
722 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset); in printOperand()
784 AMDGPU::OpName::src1)) in printOperandAndIntInputMods()
812 AMDGPU::OpName::src0); in printDPPCtrl()
992 int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en); in printExpSrcN()
995 int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr); in printExpSrcN()
1073 for (int OpName : { AMDGPU::OpName::src0_modifiers, in printPackedModifier()
1074 AMDGPU::OpName::src1_modifiers, in printPackedModifier()
1075 AMDGPU::OpName::src2_modifiers }) { in printPackedModifier()
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/netbsd-src/sys/external/bsd/acpica/dist/compiler/
H A Dasloffset.c62 char *OpName,
353 char *OpName, in LsEmitOffsetTableEntry() argument
385 Offset, ACPI_FORMAT_UINT64 (Value), OpName); in LsEmitOffsetTableEntry()

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