| /netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/ |
| H A D | InstrBuilder.cpp | 325 Write.OpIndex = i; in populateWrites()
340 dbgs() << "\t\t[Def] OpIdx=" << Write.OpIndex in populateWrites()
352 Write.OpIndex = ~CurrentDef; in populateWrites()
370 dbgs() << "\t\t[Def][I] OpIdx=" << ~Write.OpIndex in populateWrites()
379 Write.OpIndex = OptionalDefIdx; in populateWrites()
385 dbgs() << "\t\t[Def][O] OpIdx=" << Write.OpIndex in populateWrites()
404 for (unsigned I = 0, OpIndex = MCDesc.getNumOperands(); in populateWrites() local
405 I < NumVariadicOps && !AssumeUsesOnly; ++I, ++OpIndex) { in populateWrites()
406 const MCOperand &Op = MCI.getOperand(OpIndex); in populateWrites()
411 Write.OpIndex = OpIndex; in populateWrites()
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| H A D | Instruction.cpp | 126 dbgs() << "{ OpIdx=" << WD->OpIndex << ", Lat=" << getLatency() << ", RegID " in dump()
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| /netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | PredicateExpander.cpp | 21 void PredicateExpander::expandCheckImmOperand(raw_ostream &OS, int OpIndex, in expandCheckImmOperand() argument
26 OS << "MI" << (isByRef() ? "." : "->") << "getOperand(" << OpIndex in expandCheckImmOperand()
33 void PredicateExpander::expandCheckImmOperand(raw_ostream &OS, int OpIndex, in expandCheckImmOperand() argument
37 expandCheckImmOperandSimple(OS, OpIndex, FunctionMapper); in expandCheckImmOperand()
41 OS << "MI" << (isByRef() ? "." : "->") << "getOperand(" << OpIndex in expandCheckImmOperand()
49 int OpIndex, in expandCheckImmOperandSimple() argument
55 OS << "MI" << (isByRef() ? "." : "->") << "getOperand(" << OpIndex in expandCheckImmOperandSimple()
61 void PredicateExpander::expandCheckRegOperand(raw_ostream &OS, int OpIndex, in expandCheckRegOperand() argument
68 OS << "MI" << (isByRef() ? "." : "->") << "getOperand(" << OpIndex in expandCheckRegOperand()
81 int OpIndex, in expandCheckRegOperandSimple() argument
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| H A D | PredicateExpander.h | 58 void expandCheckImmOperand(raw_ostream &OS, int OpIndex, int ImmVal,
60 void expandCheckImmOperand(raw_ostream &OS, int OpIndex, StringRef ImmVal,
62 void expandCheckImmOperandSimple(raw_ostream &OS, int OpIndex,
64 void expandCheckRegOperand(raw_ostream &OS, int OpIndex, const Record *Reg,
66 void expandCheckRegOperandSimple(raw_ostream &OS, int OpIndex,
77 void expandCheckIsRegOperand(raw_ostream &OS, int OpIndex);
78 void expandCheckIsImmOperand(raw_ostream &OS, int OpIndex);
79 void expandCheckInvalidRegOperand(raw_ostream &OS, int OpIndex);
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| H A D | AsmWriterEmitter.cpp | 739 int OpIndex, PrintIndex; in formatAliasString() local
740 std::tie(OpIndex, PrintIndex) = getOpData(Name); in formatAliasString()
743 OS << format("\\x%02X", (unsigned char)OpIndex + 1); in formatAliasString()
748 OS << format("\\xFF\\x%02X\\x%02X", OpIndex + 1, PrintIndex + 1); in formatAliasString()
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| /netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/ |
| H A D | MCInstrDescView.cpp | 110 unsigned OpIndex = 0; in create() local
113 for (; OpIndex < Description->getNumOperands(); ++OpIndex) { in create()
114 const auto &OpInfo = Description->opInfo_begin()[OpIndex]; in create()
116 Operand.Index = OpIndex; in create()
117 Operand.IsDef = (OpIndex < Description->getNumDefs()); in create()
121 int TiedToIndex = Description->getOperandConstraint(OpIndex, MCOI::TIED_TO); in create()
132 MCPhysReg && *MCPhysReg; ++MCPhysReg, ++OpIndex) { in create()
134 Operand.Index = OpIndex; in create()
141 MCPhysReg && *MCPhysReg; ++MCPhysReg, ++OpIndex) { in create()
143 Operand.Index = OpIndex; in create()
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| H A D | Assembler.cpp | 98 for (unsigned OpIndex = 0, E = Inst.getNumOperands(); OpIndex < E; in addInstruction() local
99 ++OpIndex) { in addInstruction()
100 const MCOperand &Op = Inst.getOperand(OpIndex); in addInstruction()
102 const bool IsDef = OpIndex < MCID.getNumDefs(); in addInstruction()
104 const MCOperandInfo &OpInfo = MCID.operands().begin()[OpIndex]; in addInstruction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsELFStreamer.cpp | 43 for (unsigned OpIndex = 0; OpIndex < Inst.getNumOperands(); ++OpIndex) { in emitInstruction() local
44 const MCOperand &Op = Inst.getOperand(OpIndex); in emitInstruction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MCA/ |
| H A D | Instruction.h | 41 int OpIndex; member
61 bool isImplicitWrite() const { return OpIndex < 0; }; in isImplicitWrite()
69 int OpIndex; member
79 bool isImplicitRead() const { return OpIndex < 0; }; in isImplicitRead()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| H A D | TypeBasedAliasAnalysis.cpp | 298 unsigned OpIndex = FirstFieldOpNo + FieldIndex * NumOpsPerField; in getFieldType() local
299 auto *TypeNode = cast<MDNode>(getNode()->getOperand(OpIndex)); in getFieldType()
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| H A D | ScalarEvolution.cpp | 6372 for (unsigned OpIndex = 0; OpIndex < I->getNumOperands(); ++OpIndex) { in isSCEVExprNeverPoison() local
6375 if (!isSCEVable(I->getOperand(OpIndex)->getType())) in isSCEVExprNeverPoison()
6377 const SCEV *Op = getSCEV(I->getOperand(OpIndex)); in isSCEVExprNeverPoison()
6382 if (OtherOpIndex != OpIndex) { in isSCEVExprNeverPoison()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | 1568 unsigned OpIndex; in selectDivRem() local
1573 OpIndex = 0; in selectDivRem()
1576 OpIndex = 1; in selectDivRem()
1579 OpIndex = 2; in selectDivRem()
1582 OpIndex = 3; in selectDivRem()
1587 const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex]; in selectDivRem()
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| H A D | X86FastISel.cpp | 1932 unsigned TypeIndex, OpIndex; in X86SelectDivRem() local
1946 case Instruction::SDiv: OpIndex = 0; break; in X86SelectDivRem()
1947 case Instruction::SRem: OpIndex = 1; break; in X86SelectDivRem()
1948 case Instruction::UDiv: OpIndex = 2; break; in X86SelectDivRem()
1949 case Instruction::URem: OpIndex = 3; break; in X86SelectDivRem()
1953 const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex]; in X86SelectDivRem()
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| H A D | X86ISelLowering.cpp | 17628 unsigned OpIndex = i / 2; in lowerV4X128Shuffle() local
17629 if (Ops[OpIndex].isUndef()) in lowerV4X128Shuffle()
17630 Ops[OpIndex] = Op; in lowerV4X128Shuffle()
17631 else if (Ops[OpIndex] != Op) in lowerV4X128Shuffle()
35670 unsigned OpIndex = i / 2; in combineX86ShuffleChain() local
35671 if (Ops[OpIndex].isUndef()) in combineX86ShuffleChain()
35672 Ops[OpIndex] = Op; in combineX86ShuffleChain()
35673 else if (Ops[OpIndex] != Op) in combineX86ShuffleChain()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 461 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI); in getSingleInstruction() local
462 MCOperand &MCO = MI.getOperand(OpIndex); in getSingleInstruction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 3612 int OpIndex; in orderFrameObjects() local
3616 OpIndex = 3; in orderFrameObjects()
3622 OpIndex = 1; in orderFrameObjects()
3625 OpIndex = -1; in orderFrameObjects()
3629 if (OpIndex >= 0) { in orderFrameObjects()
3630 const MachineOperand &MO = MI.getOperand(OpIndex); in orderFrameObjects()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/ |
| H A D | TargetInstrPredicate.td | 92 int OpIndex = Index;
|