Searched refs:Op1VT (Results 1 – 3 of 3) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 14292 EVT Op1VT = N->getOperand(1).getValueType(); in combineStoreFPToInt() local
14300 (Op1VT == MVT::i32 || Op1VT == MVT::i64 || in combineStoreFPToInt()
14301 (Subtarget.hasP9Vector() && (Op1VT == MVT::i16 || Op1VT == MVT::i8))); in combineStoreFPToInt()
14326 unsigned ByteSize = Op1VT.getScalarSizeInBits() / 8; in combineStoreFPToInt()
14329 DAG.getValueType(Op1VT) }; in combineStoreFPToInt()
14729 EVT Op1VT = N->getOperand(1).getValueType(); in PerformDAGCombine() local
14748 (Op1VT == MVT::i32 || Op1VT == MVT::i16 || in PerformDAGCombine()
14749 (Subtarget.hasLDBRX() && Subtarget.isPPC64() && Op1VT == MVT::i64))) { in PerformDAGCombine()
14764 if (Op1VT.bitsGT(mVT)) { in PerformDAGCombine()
14765 int Shift = Op1VT.getSizeInBits() - mVT.getSizeInBits(); in PerformDAGCombine()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 8645 EVT Op1VT = V1.getValueType(); in LowerCONCAT_VECTORS_i1() local
8649 assert(Op1VT == Op2VT && "Operand types don't match!"); in LowerCONCAT_VECTORS_i1()
8655 SDValue NewV1 = PromoteMVEPredVector(dl, V1, Op1VT, DAG); in LowerCONCAT_VECTORS_i1()
8722 EVT Op1VT = V1.getValueType(); in LowerEXTRACT_SUBVECTOR() local
8731 SDValue NewV1 = PromoteMVEPredVector(dl, V1, Op1VT, DAG); in LowerEXTRACT_SUBVECTOR()
9051 EVT Op1VT = Op1.getValueType(); in LowerMUL() local
9054 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), in LowerMUL()
9056 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); in LowerMUL()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 3735 EVT Op1VT = Op1.getValueType(); in LowerMUL() local
3738 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), in LowerMUL()
3740 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); in LowerMUL()
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