| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMHazardRecognizer.cpp | 190 int64_t Offset0 = 0; in getHazardType() local
208 Ptr0 = GetPointerBaseWithConstantOffset(BaseVal0, Offset0, DL, true); in getHazardType()
211 return CheckOffsets(Offset0, Offset1); in getHazardType()
220 Offset0 = MF.getFrameInfo().getObjectOffset(FS0->getFrameIndex()); in getHazardType()
222 return CheckOffsets(Offset0, Offset1); in getHazardType()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 180 bool isDSOffset2Legal(SDValue Base, unsigned Offset0, unsigned Offset1,
183 bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
185 bool SelectDS128Bit8ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
187 bool SelectDSReadWrite2(SDValue Ptr, SDValue &Base, SDValue &Offset0,
1278 bool AMDGPUDAGToDAGISel::isDSOffset2Legal(SDValue Base, unsigned Offset0, in isDSOffset2Legal() argument
1281 if (Offset0 % Size != 0 || Offset1 % Size != 0) in isDSOffset2Legal()
1283 if (!isUInt<8>(Offset0 / Size) || !isUInt<8>(Offset1 / Size)) in isDSOffset2Legal()
1297 SDValue &Offset0, in SelectDS64Bit4ByteAligned() argument
1299 return SelectDSReadWrite2(Addr, Base, Offset0, Offset1, 4); in SelectDS64Bit4ByteAligned()
1303 SDValue &Offset0, in SelectDS128Bit8ByteAligned() argument
[all …]
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| H A D | AMDGPUInstructionSelector.h | 217 bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
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| H A D | SIInstrInfo.cpp | 130 int64_t &Offset0, in areLoadsFromSameBasePtr() argument
166 Offset0 = cast<ConstantSDNode>(Load0->getOperand(Offset0Idx))->getZExtValue(); in areLoadsFromSameBasePtr()
191 Offset0 = Load0Offset->getZExtValue(); in areLoadsFromSameBasePtr()
224 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue(); in areLoadsFromSameBasePtr()
282 unsigned Offset0 = Offset0Op->getImm(); in getMemOperandsWithOffsetWidth() local
284 if (Offset0 + 1 != Offset1) in getMemOperandsWithOffsetWidth()
303 Offset = EltSize * Offset0; in getMemOperandsWithOffsetWidth()
471 int64_t Offset0, int64_t Offset1, in shouldScheduleLoadsNear() argument
473 assert(Offset1 > Offset0 && in shouldScheduleLoadsNear()
479 return (NumLoads <= 16 && (Offset1 - Offset0) < 64); in shouldScheduleLoadsNear()
[all …]
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| H A D | AMDGPUInstructionSelector.cpp | 1268 unsigned Offset0 = OrderedCountIndex << 2; in selectDSOrderedIntrinsic() local
1275 unsigned Offset = Offset0 | (Offset1 << 8); in selectDSOrderedIntrinsic()
3792 bool AMDGPUInstructionSelector::isDSOffset2Legal(Register Base, int64_t Offset0, in isDSOffset2Legal() argument
3795 if (Offset0 % Size != 0 || Offset1 % Size != 0) in isDSOffset2Legal()
3797 if (!isUInt<8>(Offset0 / Size) || !isUInt<8>(Offset1 / Size)) in isDSOffset2Legal()
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| H A D | SIInstrInfo.h | 198 bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
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| H A D | SIInstrInfo.td | 1099 def offset0 : NamedOperandU8<"Offset0", NamedMatchClass<"Offset0">>;
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| H A D | SIISelLowering.cpp | 6846 unsigned Offset0 = OrderedCountIndex << 2; in LowerINTRINSIC_W_CHAIN() local
6853 unsigned Offset = Offset0 | (Offset1 << 8); in LowerINTRINSIC_W_CHAIN()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 347 int64_t Offset0; in apply() local
349 MachineOperand *BaseOp0 = HII.getBaseAndOffset(L0, Offset0, Size0); in apply()
368 if (((Offset0 ^ Offset1) & 0x18) != 0) in apply()
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| H A D | HexagonISelLoweringHVX.cpp | 1729 SDValue Offset0 = DAG.getTargetConstant(0, dl, ty(Base)); in LowerHvxMaskedOp() local
1733 {Mask, Base, Offset0, Value, Chain}, DAG); in LowerHvxMaskedOp()
1760 {MaskU.first, Base, Offset0, ValueU.first, Chain}, DAG); in LowerHvxMaskedOp()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 15264 const APInt &Offset0 = CN->getAPIntValue(); in CombineToPreIndexedLoadStore() local
15273 APInt CNV = Offset0; in CombineToPreIndexedLoadStore()
17384 int64_t Offset0 = LoadNodes[0].OffsetFromBase; in tryStoreMergeOfLoads() local
17387 if (Offset0 - Offset1 == ElementSizeBytes && in tryStoreMergeOfLoads()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 7764 bool Offset0 = false, Offset1 = false; in getFauxShuffleMask() local
7776 Offset0 = true; in getFauxShuffleMask()
7801 if (Offset0 || Offset1) { in getFauxShuffleMask()
7803 if ((Offset0 && isInRange(M, 0, NumElts)) || in getFauxShuffleMask()
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