| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86ShuffleDecode.cpp | 149 unsigned NumLanes = Size / 128; in DecodePSHUFMask() local
150 if (NumLanes == 0) NumLanes = 1; // Handle MMX in DecodePSHUFMask()
151 unsigned NumLaneElts = NumElts / NumLanes; in DecodePSHUFMask()
220 unsigned NumLanes = (NumElts * ScalarBits) / 128; in DecodeUNPCKHMask() local
221 if (NumLanes == 0) NumLanes = 1; // Handle MMX in DecodeUNPCKHMask()
222 unsigned NumLaneElts = NumElts / NumLanes; in DecodeUNPCKHMask()
236 unsigned NumLanes = (NumElts * ScalarBits) / 128; in DecodeUNPCKLMask() local
237 if (NumLanes == 0 ) NumLanes = 1; // Handle MMX in DecodeUNPCKLMask()
238 unsigned NumLaneElts = NumElts / NumLanes; in DecodeUNPCKLMask()
266 unsigned NumLanes = NumElts / NumElementsInLane; in decodeVSHUF64x2FamilyMask() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 288 unsigned NumLanes = Size / 4; in allocateSGPRSpillToVGPR() local
290 if (NumLanes > WaveSize) in allocateSGPRSpillToVGPR()
298 for (unsigned I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) { in allocateSGPRSpillToVGPR()
378 unsigned NumLanes = Size / 4; in allocateVGPRSpillToAGPR() local
379 Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister); in allocateVGPRSpillToAGPR()
407 for (unsigned I = 0; I < NumLanes; ++I) { in allocateVGPRSpillToAGPR()
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| H A D | AMDGPURegisterBankInfo.cpp | 1940 unsigned NumLanes = DstRegs.size(); in foldExtractEltToCmpSelect() local
1941 if (!NumLanes) in foldExtractEltToCmpSelect()
1942 NumLanes = 1; in foldExtractEltToCmpSelect()
1947 SmallVector<Register, 2> Res(NumLanes); in foldExtractEltToCmpSelect()
1948 for (unsigned L = 0; L < NumLanes; ++L) in foldExtractEltToCmpSelect()
1957 for (unsigned L = 0; L < NumLanes; ++L) { in foldExtractEltToCmpSelect()
1959 UnmergeToEltTy.getReg(I * NumLanes + L), Res[L]); in foldExtractEltToCmpSelect()
1968 for (unsigned L = 0; L < NumLanes; ++L) { in foldExtractEltToCmpSelect()
1969 Register DstReg = (NumLanes == 1) ? MI.getOperand(0).getReg() : DstRegs[L]; in foldExtractEltToCmpSelect()
2025 unsigned NumLanes = InsRegs.size(); in foldInsertEltToCmpSelect() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86MCInstLower.cpp | 2225 int NumLanes = 1; in addConstantComments() local
2228 case X86::VBROADCASTF128: NumLanes = 2; break; in addConstantComments()
2229 case X86::VBROADCASTI128: NumLanes = 2; break; in addConstantComments()
2230 case X86::VBROADCASTF32X4Z256rm: NumLanes = 2; break; in addConstantComments()
2231 case X86::VBROADCASTF32X4rm: NumLanes = 4; break; in addConstantComments()
2232 case X86::VBROADCASTF32X8rm: NumLanes = 2; break; in addConstantComments()
2233 case X86::VBROADCASTF64X2Z128rm: NumLanes = 2; break; in addConstantComments()
2234 case X86::VBROADCASTF64X2rm: NumLanes = 4; break; in addConstantComments()
2235 case X86::VBROADCASTF64X4rm: NumLanes = 2; break; in addConstantComments()
2236 case X86::VBROADCASTI32X4Z256rm: NumLanes = 2; break; in addConstantComments()
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| H A D | X86InstCombineIntrinsic.cpp | 449 unsigned NumLanes = ResTy->getPrimitiveSizeInBits() / 128; in simplifyX86pack() local
454 unsigned NumSrcEltsPerLane = NumSrcElts / NumLanes; in simplifyX86pack()
492 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in simplifyX86pack()
1954 unsigned NumLanes = Ty0->getPrimitiveSizeInBits() / 128; in simplifyDemandedVectorEltsIntrinsic() local
1955 unsigned VWidthPerLane = VWidth / NumLanes; in simplifyDemandedVectorEltsIntrinsic()
1956 unsigned InnerVWidthPerLane = InnerVWidth / NumLanes; in simplifyDemandedVectorEltsIntrinsic()
1964 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in simplifyDemandedVectorEltsIntrinsic()
1979 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in simplifyDemandedVectorEltsIntrinsic()
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| H A D | X86InterleavedAccess.cpp | 481 unsigned NumLanes = std::max((int)VT.getSizeInBits() / 128, 1); in DecodePALIGNRMask() local
482 unsigned NumLaneElts = NumElts / NumLanes; in DecodePALIGNRMask()
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| H A D | X86ISelLowering.cpp | 6896 unsigned NumLanes = VT.getSizeInBits() / 128; in createPackShuffleMask() local
6903 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in createPackShuffleMask()
6916 int NumLanes = VT.getSizeInBits() / 128; in getPackDemandedElts() local
6919 int NumEltsPerLane = NumElts / NumLanes; in getPackDemandedElts()
6920 int NumInnerEltsPerLane = NumInnerElts / NumLanes; in getPackDemandedElts()
6926 for (int Lane = 0; Lane != NumLanes; ++Lane) { in getPackDemandedElts()
6941 int NumLanes = VT.getSizeInBits() / 128; in getHorizDemandedElts() local
6943 int NumEltsPerLane = NumElts / NumLanes; in getHorizDemandedElts()
10912 int NumLanes = NumElts / NumEltsPerLane; in isMultiLaneShuffleMask() local
10913 if (NumLanes > 1) { in isMultiLaneShuffleMask()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64InstPrinter.h | 153 template <unsigned NumLanes, char LaneKind>
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| H A D | AArch64InstPrinter.cpp | 1332 template <unsigned NumLanes, char LaneKind>
1337 if (NumLanes) in printTypedVectorList()
1338 Suffix += itostr(NumLanes) + LaneKind; in printTypedVectorList()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/ |
| H A D | SLPVectorizer.cpp | 938 for (unsigned Lane = 0, NumLanes = getNumLanes(); Lane != NumLanes; in clearUsed() local
1263 for (unsigned Lane = 0, NumLanes = getNumLanes(); Lane != NumLanes; in getBestLaneToStartReordering() local
1301 unsigned NumLanes = VL.size(); in appendOperandsOfVL() local
1303 OpsVec[OpIdx].resize(NumLanes); in appendOperandsOfVL()
1304 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in appendOperandsOfVL()
1392 unsigned NumLanes = getNumLanes(); in reorder() local
1451 for (unsigned Distance = 1; Distance != NumLanes; ++Distance) { in reorder()
1455 if (Lane < 0 || Lane >= (int)NumLanes) in reorder()
1458 assert(LastLane >= 0 && LastLane < (int)NumLanes && in reorder()
1685 unsigned NumLanes = Scalars.size(); in setOperandsInOrder() local
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| /netbsd-src/external/apache2/llvm/dist/clang/utils/TableGen/ |
| H A D | NeonEmitter.cpp | 767 unsigned NumLanes; in fromTypedefName() local
768 Name.substr(0, I).getAsInteger(10, NumLanes); in fromTypedefName()
770 T.Bitwidth = T.ElementBitwidth * NumLanes; in fromTypedefName()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/IR/ |
| H A D | AutoUpgrade.cpp | 2469 unsigned NumLanes = VT->getPrimitiveSizeInBits() / 128; in UpgradeIntrinsicCall() local
2471 unsigned ControlBitsMask = NumLanes - 1; in UpgradeIntrinsicCall()
2472 unsigned NumControlBits = NumLanes / 2; in UpgradeIntrinsicCall()
2475 for (unsigned l = 0; l != NumLanes; ++l) { in UpgradeIntrinsicCall()
2478 if (l >= NumLanes / 2) in UpgradeIntrinsicCall()
2479 LaneMask += NumLanes; in UpgradeIntrinsicCall()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 1982 size_t NumLanes = Op.getSimpleValueType().getVectorNumElements(); in unrollVectorShift() local
1990 for (size_t i = 0; i < NumLanes; ++i) { in unrollVectorShift()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 12435 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in performFpToIntCombine() local
12436 switch (NumLanes) { in performFpToIntCombine()
12508 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in performFDivCombine() local
12509 switch (NumLanes) { in performFDivCombine()
16310 uint64_t NumLanes = ResVT.getVectorElementCount().getKnownMinValue(); in PerformDAGCombine() local
16311 SDValue ExtIdx = DAG.getVectorIdxConstant(IdxConst * NumLanes, DL); in PerformDAGCombine()
16327 uint64_t NumLanes = in PerformDAGCombine() local
16330 if ((TupleLanes % NumLanes) != 0) in PerformDAGCombine()
16333 uint64_t NumVecs = TupleLanes / NumLanes; in PerformDAGCombine()
16340 SDValue ExtIdx = DAG.getVectorIdxConstant(I * NumLanes, DL); in PerformDAGCombine()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMInstrInfo.td | 717 class MVEVectorIndexOperand<int NumLanes> : AsmOperandClass {
718 let Name = "MVEVectorIndex"#NumLanes;
720 let PredicateMethod = "isVectorIndexInRange<"#NumLanes#">";
723 class MVEVectorIndex<int NumLanes> : Operand<i32> {
725 let ParserMatchClass = MVEVectorIndexOperand<NumLanes>;
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| H A D | ARMISelLowering.cpp | 15469 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in PerformVCVTCombine() local
15470 if (FloatBits != 32 || IntBits > 32 || (NumLanes != 4 && NumLanes != 2)) { in PerformVCVTCombine()
15489 ISD::INTRINSIC_WO_CHAIN, dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32, in PerformVCVTCombine()
15527 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in PerformVDIVCombine() local
15528 if (FloatBits != 32 || IntBits > 32 || (NumLanes != 4 && NumLanes != 2)) { in PerformVDIVCombine()
15547 dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32, in PerformVDIVCombine()
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| /netbsd-src/external/apache2/llvm/dist/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 13258 unsigned NumLanes = Ty->getPrimitiveSizeInBits() / 128; in EmitX86BuiltinExpr() local
13259 unsigned NumLaneElts = NumElts / NumLanes; in EmitX86BuiltinExpr()
13284 unsigned NumLanes = Ty->getPrimitiveSizeInBits() / 128; in EmitX86BuiltinExpr() local
13285 unsigned NumLaneElts = NumElts / NumLanes; in EmitX86BuiltinExpr()
13391 unsigned NumLanes = Ty->getPrimitiveSizeInBits() == 512 ? 4 : 2; in EmitX86BuiltinExpr() local
13392 unsigned NumLaneElts = NumElts / NumLanes; in EmitX86BuiltinExpr()
13396 unsigned Index = (Imm % NumLanes) * NumLaneElts; in EmitX86BuiltinExpr()
13397 Imm /= NumLanes; // Discard the bits we just used. in EmitX86BuiltinExpr()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2215 template <unsigned NumLanes>
2218 return VectorIndex.Val < NumLanes; in isVectorIndexInRange()
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