Searched refs:NotOpc (Results 1 – 3 of 3) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 108 unsigned NotOpc; member
125 NotOpc = AMDGPU::S_NOT_B32; in SGPRSpillBuilder()
129 NotOpc = AMDGPU::S_NOT_B64; in SGPRSpillBuilder()
204 auto I = BuildMI(MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg); in prepare()
238 auto I = BuildMI(MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg); in restore()
264 BuildMI(MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg); in readWriteTmpVGPR()
266 BuildMI(MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg); in readWriteTmpVGPR()
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| H A D | SIInstrInfo.cpp | 1757 unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64; in expandPostRAPseudo() local
1759 auto FirstNot = BuildMI(MBB, MI, DL, get(NotOpc), Exec).addReg(Exec); in expandPostRAPseudo()
1763 BuildMI(MBB, MI, DL, get(NotOpc), Exec) in expandPostRAPseudo()
1769 unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64; in expandPostRAPseudo() local
1771 auto FirstNot = BuildMI(MBB, MI, DL, get(NotOpc), Exec).addReg(Exec); in expandPostRAPseudo()
1777 BuildMI(MBB, MI, DL, get(NotOpc), Exec) in expandPostRAPseudo()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 3607 unsigned NotOpc = Pred == ICmpInst::ICMP_NE ? AArch64::NOTv8i8 : 0; in selectVectorICmp() local
3609 NotOpc = NotOpc ? AArch64::NOTv16i8 : 0; in selectVectorICmp()
3618 if (NotOpc) { in selectVectorICmp()
3619 Cmp = MIB.buildInstr(NotOpc, {DstReg}, {Cmp}); in selectVectorICmp()
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