Searched refs:NeedAlign (Results 1 – 7 of 7) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.cpp | 1939 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandStoreVec2() local 1943 auto UseAligned = [&](Align NeedAlign, Align HasAlign) { in expandStoreVec2() argument 1944 return !NeedsAligna && (NeedAlign <= HasAlign); in expandStoreVec2() 1949 StoreOpc = UseAligned(NeedAlign, HasAlign) ? Hexagon::V6_vS32b_ai in expandStoreVec2() 1960 StoreOpc = UseAligned(NeedAlign, HasAlign) ? Hexagon::V6_vS32b_ai in expandStoreVec2() 1991 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandLoadVec2() local 1995 auto UseAligned = [&](Align NeedAlign, Align HasAlign) { in expandLoadVec2() argument 1996 return !NeedsAligna && (NeedAlign <= HasAlign); in expandLoadVec2() 2000 LoadOpc = UseAligned(NeedAlign, HasAlign) ? Hexagon::V6_vL32b_ai in expandLoadVec2() 2008 LoadOpc = UseAligned(NeedAlign, HasAlign) ? Hexagon::V6_vL32b_ai in expandLoadVec2() [all …]
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| H A D | HexagonInstrInfo.cpp | 1025 auto UseAligned = [&](const MachineInstr &MI, Align NeedAlign) { in expandPostRAPseudo() argument 1028 return all_of(MI.memoperands(), [NeedAlign](const MachineMemOperand *MMO) { in expandPostRAPseudo() 1029 return MMO->getAlign() >= NeedAlign; in expandPostRAPseudo() 1089 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo() local 1090 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai in expandPostRAPseudo() 1105 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo() local 1106 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai in expandPostRAPseudo() 1127 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo() local 1128 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai in expandPostRAPseudo() 1144 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo() local [all …]
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| H A D | HexagonVectorCombine.cpp | 151 NeedAlign(HVC.getTypeAlignment(ValTy)) {} in AddrInfo() 158 Align NeedAlign; member 258 OS << "NeedAlign: " << AI.NeedAlign.value() << '\n'; in operator <<() 723 getMaxOf(MoveInfos, [](const AddrInfo &AI) { return AI.NeedAlign; }); in realignGroup() 724 Align MinNeeded = WithMaxNeeded.NeedAlign; in realignGroup()
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| H A D | HexagonISelLowering.cpp | 1916 unsigned NeedAlign) const { in validateConstPtrAlignment() 1921 unsigned HaveAlign = Addr != 0 ? 1u << countTrailingZeros(Addr) : NeedAlign; in validateConstPtrAlignment() 1922 if (HaveAlign < NeedAlign) { in validateConstPtrAlignment() 1927 << ", but the memory access requires " << NeedAlign; in validateConstPtrAlignment() 2939 unsigned NeedAlign = Subtarget.getTypeAlignment(StoreTy); in LowerStore() local 2940 if (ClaimAlign < NeedAlign) in LowerStore() 2950 unsigned NeedAlign = Subtarget.getTypeAlignment(LoadTy); in LowerUnalignedLoad() local 2952 if (HaveAlign >= NeedAlign) in LowerUnalignedLoad() 2972 if (!DoDefault && (2 * HaveAlign) == NeedAlign) { in LowerUnalignedLoad() 2989 assert(LoadTy.getSizeInBits() == 8*NeedAlign); in LowerUnalignedLoad() [all …]
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| H A D | HexagonISelLowering.h | 345 unsigned NeedAlign) const;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | RegisterScavenging.cpp | 455 Align NeedAlign = TRI->getSpillAlign(RC); in spill() local 468 if (NeedSize > S || NeedAlign > A) in spill() 476 unsigned D = (S - NeedSize) + (A.value() - NeedAlign.value()); in spill()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 1455 bool NeedAlign; // Does argument declaration specify alignment? in LowerCall() local 1464 NeedAlign = true; in LowerCall() 1479 NeedAlign = false; in LowerCall() 1541 if (NeedAlign) in LowerCall()
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