Searched refs:MidVT (Results 1 – 5 of 5) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 4366 MVT MidVT = MVT::getVectorVT(NewEltVT, OldEltsPerNewElt); in getPromotedVectorElementType() local
4367 assert(TLI.isTypeLegal(MidVT) && "unexpected"); in getPromotedVectorElementType()
4368 return MidVT; in getPromotedVectorElementType()
4779 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT); in PromoteNode() local
4784 NewOps.push_back(DAG.getNode(ISD::BITCAST, SDLoc(Op), MidVT, Op)); in PromoteNode()
4812 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT); in PromoteNode() local
4813 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements(); in PromoteNode()
4833 SDValue NewVec = DAG.getBuildVector(MidVT, SL, NewOps); in PromoteNode()
4858 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT); in PromoteNode() local
4859 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements(); in PromoteNode()
[all …]
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| H A D | LegalizeFloatTypes.cpp | 527 EVT MidVT = TLI.getTypeToTransformTo(*DAG.getContext(), MVT::f32); in SoftenFloatRes_FP16_TO_FP() local
532 SDValue Res32 = TLI.makeLibCall(DAG, RTLIB::FPEXT_F16_F32, MidVT, Op, in SoftenFloatRes_FP16_TO_FP()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 3260 EVT MidVT = VT.isVector() ? in performTruncateCombine() local
3264 EVT NewShiftVT = getShiftAmountTy(MidVT, DAG.getDataLayout()); in performTruncateCombine()
3265 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MidVT, in performTruncateCombine()
3274 SDValue ShrunkShift = DAG.getNode(Src.getOpcode(), SL, MidVT, in performTruncateCombine()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 13066 MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v4i32 : MVT::v8i16); in performConcatVectorsCombine() local
13067 SmallVector<int, 8> Mask(MidVT.getVectorNumElements()); in performConcatVectorsCombine()
13072 MidVT, dl, in performConcatVectorsCombine()
13073 DAG.getNode(ISD::BITCAST, dl, MidVT, N00), in performConcatVectorsCombine()
13074 DAG.getNode(ISD::BITCAST, dl, MidVT, N10), Mask)); in performConcatVectorsCombine()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 45226 EVT MidVT = VT.changeVectorElementType(MVT::i16); in combineTruncateWithSat() local
45227 SDValue Mid = truncateVectorWithPACK(X86ISD::PACKSS, MidVT, USatVal, DL, in combineTruncateWithSat()
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